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    請使用永久網址來引用或連結此文件: https://ir.lib.ncu.edu.tw/handle/987654321/98154


    題名: 應用於SRRC脈波成形單載波通訊之Farrow內插器設計與應用;Design and Applications of Farrow Interpolators for Single-Carrier Communication with SRRC Pulse-Shaping
    作者: 陳純政;Chen, Chun-Cheng
    貢獻者: 通訊工程學系
    關鍵詞: 脈波成形;分數延遲濾波器;內插器;Pulse Shaping;Fractional delay filter;Interpolator
    日期: 2025-08-25
    上傳時間: 2025-10-17 12:26:36 (UTC+8)
    出版者: 國立中央大學
    摘要: 低地球軌道(Low-Earth Orbit, LEO)衛星通訊通道具有時變延遲、訊號強度衰減以及都卜勒頻移等特性。由於 LEO 衛星距地球較近,訊號傳輸延遲低,因此特別適合應用於衛星網際網路。然而,低軌道衛星必須以較高的軌道速度繞地運行,致使衛星與地面站之間的距離隨時間快速變化,進而導致訊號傳輸延遲呈現連續時變的特性。為了開發能適應此類通道特性的通訊收發機,需要設計一個能夠真實模擬 LEO 通道效應的通道模擬器,以便有效驗證收發機的性能,並提升其在實際運作環境中的可靠性。基於以上需求,我們首先探討了Farrow 結構的可變分數延遲濾波器的設計。此濾波器是 LEO 通道模擬器中的關鍵元件,可在DSP有效實現連續時變延遲效應。與其他分數延遲濾波器採用頻域設計的方法不同,本論文提出的 Farrow 結構內插器是採用時域上最小ISI效能(RC波形)設計,實現SRRC波形的分數取樣週期的延遲。最後,將設計的Farrow 結構內插器應用於符碼間時序同步(Symbol-Timing Synchronization)與任意符碼率轉換(Arbitray Symbol Rate Converter)上。;Low-Earth Orbit (LEO) satellite communication channels are characterized by time-varying propagation delays, signal attenuation, and Doppler frequency shifts. Owing to the proximity of LEO satellites to the Earth’s surface, they offer high signal transmission speeds and low latency, making them particularly well-suited for applications such as satellite internet. However, LEO satellites must operate at high orbital velocities to maintain their trajectories, causing the distance between the satellite and ground stations to change rapidly over time. This results in continuously time-varying propagation delays.
    To enable communication transceivers to operate reliably under such challenging channel conditions, it is crucial to design a channel emulator capable of accurately replicating the effects of a LEO satellite link. Such an emulator allows rigorous validation of transceiver performance and enhances robustness in practical deployment scenarios.
    In response to these challenges, this paper investigates the design of a Farrow-structured variable fractional delay filter, a critical component of the LEO channel emulator for efficiently realizing continuously time-varying delays in digital signal processing (DSP). Unlike conventional fractional delay filters designed in the frequency domain, the proposed Farrow-structured interpolator is optimized in the time domain based on the minimum inter-symbol interference (ISI) performance criterion of a raised-cosine (RC) pulse. This approach enables precise fractional-sample delays for signals shaped with square-root raised cosine (SRRC) filtering. Finally, the designed Farrow-structured interpolator is applied to symbol timing synchronization and arbitrary symbol rate conversion in SRRC-based transceivers.
    顯示於類別:[通訊工程研究所] 博碩士論文

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