本論文呈現模擬非屏蔽雙絞乙太網路線傳輸訊號時遭遇射頻干擾(RFI)所受到的影響，由於本系統所傳輸的訊號根據網路通訊所規定的規格 IEEE 802.3bz™-2016 規範下，使用 PAM-2 及 PAM-16 編碼進行訊號傳輸，而若將未消除射頻干擾的訊號送至等化器(Equalizer)，等化器將無法正常還原傳送端訊號，因此需透過數位射頻干擾消除器(Digital Radio Frequency Interference Canceller)與本研究所提出之頻域自適應演算法，於等化器之前將干擾有效消除。 本篇共提出兩種頻域自適應演算法皆基於最小均方根演算法(LMS)改良設計，一種為峰值選取頻域正規化最小均方根演算法(Peak-select Frequency domain Normalized Least Mean Square )是為了對射頻干擾做初步的消除，來使後續的等化器能正確的收斂，另一種演算法為峰值選取頻域決策導向正規化最小均方根演算法(Peak-select Frequency domain Decision Direct Normalized Least Mean Square )是在考量等化器收斂之後，使用決策誤差來令數位射頻干擾消除器的權重係數收斂的更精準，進一步提升射頻干擾的消除效果，然而該演算法需要對其中的參數去設定，本論文針對此參數進行模擬及探討，最後也有結合模擬數位射頻干擾消除器及等化器去對不同長度的通道及不同頻率的射頻干擾去做模擬，並驗證其系統的位元錯誤率(Bit Error Rate)是否符合規範。 在硬體的部分由於整體系統太過龐大，因此只實現數位射頻干擾消除器及第一種演算法，並將其分為五塊去實現，整體的電路架構以管線化(pipeline)進行設計，先使用 Verilog描述與模擬，接著透過晶片設計工具 Design Compiler 與 IC Compiler 在 TSMC-40nm 製程下驗證其電路功能。 ;This thesis studies the impact of Radio Frequency Interference (RFI) on signal transmission over Unshielded Twisted Pair (UTP) Ethernet cables compliant with IEEE 802.3bz™-2016, using PAM-2 and PAM-16 encoding schemes. Without interference mitigation, RFI-affected signals directly fed to the Equalizer hinder accurate signal recovery. To address this, a Digital RFI Canceller incorporating two proposed frequency-domain adaptive algorithms is introduced to suppress interference before equalization. Both algorithms are based on enhancements to the Least Mean Square (LMS) method. The first, Peak-select Frequency Domain Normalized LMS, provides initial RFI suppression to ensure proper Equalizer convergence. The second, Peak-select Frequency Domain Decision Direct Normalized LMS, refines interference cancellation by utilizing decision errors post-equalization, improving weight adjustments for better RFI mitigation. Parameter optimization is analyzed via simulations. System-level simulations under various channel lengths and RFI frequencies confirm that the system’s Bit Error Rate (BER) meets required standards. Due to system complexity, hardware implementation focuses only on the Canceller and the first algorithm. The design adopts a five-module pipeline structure, described and simulated in Verilog, with functional verification conducted using Design Compiler and IC Compiler under TSMC 40nm process technology.
