在現今有線通訊系統(Wireline Communication System)收發應用中，強調希望在高速傳輸下依然能維持良好的訊號品質，以利後端接收器(Receiver, RX)進行訊號還原與處理等任務，而傳送端(Transmitter, TX)經過通道(Channel)時將產生如高頻振幅衰減(Amplitude Attenuation)等諸多非理想效應，造成訊號失真，如何在接收端有效避免衰減現象，提升訊號解析(resolution)能力即是本論文著重之設計重點。 本論文提出一款接收端具抗振幅衰減及寬頻類比濾波器架構，適用於IEEE 802.3bz™-2016乙太網路規格，並設有可程式化(programmability)機制以補償不同通道長度下之振幅衰減，增強濾波器使用效率，達成終端高解析度、高線性度(linearity)之訊號輸送能力。 本論文使用TSMC 40nm CMOS製程進行設計，晶片面積為0.28 mm2，操作電壓為0.9 V，整體功率消耗(power consumption)為19.42 mW，濾波器頻寬(Bandwidth, BW)達到341 MHz，訊號對雜訊失真比(Signal-to-Noise-and-Distortion Ratio, SNDR)為81.86 dB，有效位元數(Effective Number of Bits, ENOB)為13.31 bits，最大補償增益為10.67 dB。;In wired-based communication applications nowadays, it is emphasized that good signal quality can be maintained under high-speed transmission to facilitate the back-end receiver to perform tasks such as signal restoration and processing. However, when the transmitter passes through the channel, high-frequency amplitude attenuation will occur. Many other non-ideal effects cause signal distortion. How to avoid the attenuation of the receiver effectively and the capability of improving signal analysis is the focus of this thesis′s design. This thesis proposes a receiving end analog filter architecture with anti-amplitude attenuation and wide-bandwidth, which is suitable for IEEE 802.3bz™-2016 Ethernet specifications and has a programmable mechanism to compensate for amplitude attenuation under different channel lengths. This helps to enhance filter usage efficiency and achieve high-resolution, high-linearity signal transmission capabilities. This thesis uses the TSMC 40nm CMOS process for design. The chip area is 0.28 mm2, the supply voltage is 0.9 V, the overall power consumption is 19.42 mW, the filter′s bandwidth reaches to 341 MHz, the signal-to-noise-and-distortion ratio(SNDR) is 81.86 dB, the effective number of bits(ENOB) is 13.31 bits, and the maximum compensation gain is 10.67 dB.
