在現今階層式系統晶片（System-on-Chip, SoC）設計中，為了實現不同模組之間的跨模組連線，常會在區塊中插入穿越式走線（feedthrough net）來傳遞訊號。然而，這些連線雖然有助於維持模組間的互聯，但也會額外占用區塊內部的繞線資源，進一步惡化區域性的繞線壅塞問題。儘管穿越連線對整體可繞性（routability）有明顯影響，現有文獻卻較少針對「單一區塊內」的穿越連線腳位配置問題進行深入探討。 本論文提出一套具備壅塞考量的穿越式走線腳位配置最佳化框架。該方法將此問題建模為非線性最佳化問題，並透過梯度下降演算法（gradient descent approach）進行迭代式優化。在此框架中，我們設計了一項名為 FCAM（Feedthrough Congestion Avoidance Metric）的評估指標，用以量化穿越連線路徑經過區域的壅塞程度，並據以調整腳位位置，讓穿越路徑盡可能避開壅塞嚴重的區域，達到減輕壅塞的目的。 本方法可在考量設計限制的前提下，對穿越連線腳位進行精細調整，有效提升設計的可繞性且不會造成明顯的繞線繞遠。實驗採用 12 奈米製程的工業級 SoC 進行驗證，結果顯示，本框架相較於頂層初始腳位配置，可使總溢出量（Total Overflow）降低 5.5% 至 9.0%，平均改善達 7.6%。此外，本方法亦優於隨機模擬退火法（Simulated Annealing）與商用 EDA 工具內建腳位配置功能，分別可達到約 4% 與 3% 的溢出量改善，證實所提出之方法在階層式實體設計中具實用性與效能優勢。;In modern hierarchical System-on-Chip (SoC) designs, feedthrough nets are special inter-block connections that pass through intermediate blocks to enable signal transmission across non-adjacent modules. Feedthrough insertion is essential for establishing such cross-block connectivity, but it also introduces additional routing overhead within the traversed blocks, often exacerbating local routing congestion. Despite its impact on routability, the problem of feedthrough pin assignment for congestion mitigation has received limited attention in prior research, especially at the single-block level. This thesis presents a congestion-aware pin assignment framework for feedthrough nets. The proposed method formulates the problem as a non-linear optimization task, where feedthrough pin positions are iteratively adjusted using a gradient descent approach. A key component of the framework is the Feedthrough Congestion Avoidance Metric (FCAM), which evaluates the congestion severity along the routing paths of feedthrough nets. Based on this evaluation, pin positions are refined to guide feedthrough routing away from highly congested regions, thereby alleviating internal congestion. The proposed method effectively refines feedthrough pin locations under design constraints, improving routability without introducing significant detours. Experimental results on industrial SoC benchmarks with 12nm technology demonstrate that the framework reduces total overflow (TOF) by 5.5% to 9.0%, averaging 7.6%, compared to initial top-level pin assignments. It also outperforms both a simulated annealing–based approach and a commercial EDA tool, achieving 3% and 4% lower TOF, respectively. These results confirm the effectiveness of congestion-aware feedthrough pin assignment as a practical strategy for enhancing routability in hierarchical physical design.
