| 摘要: | 本篇論文主要包含三個使用TSMC 90 nm GUTM CMOS process的電路。第一章主要講述關於近年來無線通訊的演變，與無線通訊在頻寬提升所面臨的挑戰。以此為主要觀點並講述研究動機並回顧近年來相關領域的研究進展。隨著對於無線通訊的發展，對數據傳輸速度和頻寬的需求日益增加，如5 G通訊、互聯網與自動駕駛技術，透過對操作頻率的提升，實現較快的資料傳輸速度與頻寬。而為了有更好的特性，往往需要使用先進製程來實現，先進製程本身有較好的元件特性，但其帶來研究與製作成本較高。本篇論文主要在於透過其他技術來提升特性或對操作頻率的提升。
第二章為W頻段的串接式鎖相迴路，其中Ka頻段的鎖相迴路作為W頻段的注入鎖定正交振盪器的注入信號源。通過電路的整合設計，實現了W頻段的串接式鎖相迴路。為了能夠實現低直流功耗與高操作頻率的注入鎖定正交振盪器，透過疊接增強（stacked-boosting）技術進行設計，在TSMC 90 nm GUTM CMOS製程的最高振盪頻率 150 GHz實現100至110 GHz的操作頻率，並且將緩衝放大器整合於W頻段的注入鎖定正交振盪器與Ka頻段的鎖相迴路，兩者間使用緩衝放大器對Ka頻段的輸出功率提升，已達到倍頻器所需要的輸入功率。整體電路的操作頻率為103.8至104.3 GHz。量測的相位雜訊在1 MHz偏移處低於-82 dBc/Hz，並且從1 kHz到10 MHz的方均根抖動量約為500 fs。
第三章為V頻段CMOS六階次諧波注入鎖定壓控振盪器（SILVCO）與頻率跟蹤迴路（FTL）的設計與分析。為了進一步提升注入鎖定的諧波數與鎖定頻寬，本章提出在SILVCO中使用串接式耦合注入器。本章詳細介紹了所提電路的設計方法論，並提供相關分析與模擬結果。在注入諧波倍數為6的條件下，直流功耗為23 mW，量測的操作頻率範圍為50.8至53.4 GHz，差分輸出功率接近0 dBm。量測的相位雜訊在1 MHz偏移處低於-109.4 dBc/Hz，並且從1 kHz到10 MHz的方均根抖動量小於43 fs。
第四章為一V頻段次諧波注入鎖定正交壓控振盪器（SILQVCO），並將其整合至使用自適應技術和反射型調變器的高速IQ調變器中。該SILQVCO採用了疊接增強（stacked-boosting）和變壓器耦合（transformer-coupled）技術，確保在V頻段穩定振盪並實現低直流功耗。自適應技術結合注入鎖定技術、頻率檢測器和電壓-電流轉換器（V/I converter）以改善相位雜訊。當注入諧波數為3並且使用單端注入時，其操作頻率範圍為49至50.8 GHz。量測的相位雜訊在1 MHz偏移處低於-109 dBc/Hz，並且從1 kHz到10 MHz的方均根抖動量小於51.6 fs。正交輸出的相位誤差和幅度誤差分別低於5.3°和8.9%。在正交調變（QAM）應用中，該電路支持 64-QAM 調變，展現其在先進通信系統中的應用潛力。
;This thesis primarily covers three circuits fabricated using the TSMC 90 nm GUTM CMOS process. Chapter 1 details the recent evolution of wireless communications and the challenges posed by increasing bandwidth requirements. With this perspective, it discusses the research motivations and reviews recent developments in related fields. As wireless communications continue to advance, there is a growing demand for higher data transmission speeds and wider bandwidths, exemplified by 5G communications, the internet, and autonomous driving technologies. Raising the operating frequency helps achieve faster data transfer rates and broader bandwidths. Although advanced semiconductor processes, which feature superior device characteristics, are often employed for better performance, such processes entail higher research and fabrication costs. Consequently, this thesis explores other techniques to enhance performance or operating frequency without relying solely on advanced manufacturing processes.
Chapter 2 focuses on a W-band cascaded phase-locked loop (PLL). A Ka-band PLL serves as the injection source for a W-band injection-locked quadrature oscillator. By designing a cascaded architecture, a W-band cascaded PLL is realized. To achieve a low-DC-power, high-frequency injection-locked quadrature oscillator, the stacked-boosting technique is utilized. Under the TSMC 90 nm GUTM CMOS process, which supports a maximum oscillation frequency of 150 GHz, the oscillator operates from 100 to 110 GHz. Additionally, a buffer amplifier is integrated between the W-band injection-locked quadrature oscillator and the Ka-band PLL to boost the Ka-band output signal, providing sufficient input power for the frequency multiplier. The overall operating frequency of the circuit is 103.8 to 104.3 GHz. The measured phase noise is below -82 dBc/Hz at a 1 MHz offset, and the RMS jitter from 1 kHz to 10 MHz is approximately 500 fs.
Chapter 3 presents the design and analysis of a V-band CMOS sextuple harmonic injection-locked voltage-controlled oscillator (SILVCO) and a frequency tracking loop (FTL). To further increase the harmonic injection order and locking bandwidth, a cascade-series coupled injector is proposed within the SILVCO. This chapter provides detailed design methodologies, along with relevant analyses and simulation results. Under the 6th order harmonic injection setting, the circuit consumes 23 mW of DC power; the measured operating frequency ranges from 50.8 to 53.4 GHz, and the differential output power is close to 0 dBm. The measured phase noise is below -109.4 dBc/Hz at a 1 MHz offset, and the RMS jitter from 1 kHz to 10 MHz is less than 43 fs.
Chapter 4 introduces a V-band sub-harmonic injection-locked quadrature voltage-controlled oscillator (SILQVCO), which is integrated into a high-speed IQ modulator employing adaptive techniques and reflective modulators. The SILQVCO uses stacked-boosting and transformer-coupled techniques to ensure stable oscillation in the V-band while maintaining low DC power consumption. Adaptive techniques, combined with injection locking, frequency detectors, and voltage-to-current (V/I) converters, improve phase noise. When the harmonic injection order is 3 and a single-ended injection scheme is used, the operating frequency ranges from 49 to 50.8 GHz. The measured phase noise is below -109 dBc/Hz at a 1 MHz offset, and the RMS jitter from 1 kHz to 10 MHz is less than 51.6 fs. The quadrature outputs exhibit phase and amplitude errors below 5.3° and 8.9%, respectively. In quadrature amplitude modulation (QAM) applications, the circuit supports 64-QAM modulation, demonstrating its potential for use in advanced communication systems. |
