| 摘要: | 本論文基於乙太網路IEEE 802.3bz™-2016 標準，設計乙太網路收發機系統，著重於自適應等化器與時序恢復系統的演算法開發與電路設計。本論文設計的等化器結合轉換域的前饋式等化器 (Feed Forward Equalizer, FFE) 與決策反饋式等化器 (Decision Feedback Equalizer, DFE) 結構，並搭配湯林森-何洛緒瑪預編碼 (Tomlinson-Harashima Precoder, THP) 技術對通道的符碼間干擾所造成的訊號失真進行補償。針對長點數轉換域濾波器所引入的大量延遲問題，本文引入濾波器分割與轉換域濾波技術結合的多延遲轉換域濾波技術，可有效降低轉換域長點數濾波的計算延遲，節省些許儲存單元。同時避免時序恢復系統閉迴路內引入大量延遲造成穩定裕度下降，讓迴路的參數設計更有彈性，同時在效能允許時，支援選擇性關閉部分濾波器組，以達到低功耗運作。
此外，為加速系統收斂，本論文在自適應濾波器演算法中整合了正規化技術。有別於傳統正規化運算，本文提出基於複數平面幾何的三角函數運算方式，並結合座標旋轉數位計算機 (Coordinate Rotation Digital Computer, CORDIC) 實現正規化。與傳統採用CORDIC作為除法器的方案相比，本論文提出的基於三角運算的CORDIC架構，能以近乎一半的硬體成本達到相同的正規化效果。
為了解決收發機通訊兩端使用不同的時鐘時脈當作參考造成時序不匹配的問題，加入時序恢復系統，採用穆勒與姆勒時序誤差偵測器 (Mueller and Muller Timing Error Detector, MMTED)，並與等化器迴路隔離為獨立迴路，避免等化器與時序恢復系統相互干擾效應。最終以程式語言及硬體描述語言進行系統數位電路行為建模，將兩者結果比對確認一致性後，則透過標準元件電路設計流程，使用 TSMC TN40G 製程透過 Design Compiler 進行電路邏輯合成，最後透過 IC Compiler 進行晶片的布局與繞線，並以模擬以及時序報告確認電路滿足約束條件。
;This thesis presents an Ethernet transceiver system design compliant with the IEEE 802.3bz™-2016 standard, emphasizing algorithm and circuit development for adaptive equalization and timing recovery. The equalizer combines a transfer-domain Feed-Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE), with Tomlinson-Harashima Precoder (THP) technology, to mitigate channel-induced Inter-Symbol Interference (ISI). To address latency from long-tap transfer-domain filters, a multi-delay transfer-domain filtering technique, merging filter partitioning and transfer-domain filtering, is introduced. This reduces computational latency and storage, preserves timing recovery stability margins, allows flexible loop parameter design, and supports selective filter bank deactivation for low-power operation.
For accelerated system convergence, normalization is integrated into adaptive filter algorithms. A novel CORDIC-based normalization using complex-plane trigonometric operations is proposed, achieving equivalent efficacy to traditional CORDIC-divider schemes with approximately 50% less hardware.
Furthermore, a timing recovery system employing the Mueller and Muller Timing Error Detector (MMTED), isolated from the equalizer loop to prevent adverse interactions, resolves clock mismatches. The system′s digital circuit behavior, modeled and verified, was synthesized (Design Compiler) and physically designed (IC Compiler) using the TSMC TN40G process. Simulations and timing analyses confirm adherence to design constraints. |
