| 摘要: | 此次論文研究方向為X頻段與Ku頻段的高效率寬頻功率放大器。分別使用0.18-μm CMOS、0.25-μm GaN/SiC HEMT與0.15-μm InGaAs pHEMT，分別進行X頻段連續F類模式功率放大器、X頻段連續J類模式功率放大器，與Ku頻段輸出匹配使用電抗補償與級間匹配採用濾波器的寬頻放大器。
第二章為0.18-μm CMOS製程應用在X頻段的功率放大器，輸出匹配網路採用連續F類模式，希望可以達到二倍頻接近短路，三倍頻接近開路，以達到抑制奇次諧波項的效果，從而提升效率，並且使用疊接的方式，提高電路增益與輸出功率。量測最大增益為11.4 dB，3-dB頻寬為 8.2-13.8 GHz，比例頻寬為26%，1-dB增益壓縮點之輸出功率約為 18.1 dBm，飽和輸出功率為 21.0 dBm，最大功率附加效率為 31.92 %。於9 GHz下使用LTE 16 QAM，調變頻寬為1.4 MHz。於能測量到最大輸出功率時，平均輸出功率為18.7 dBm，加入DPD後，整體相鄰通道功率比由25.6降至28.8，誤差向量幅度由9.22%降至2.87%。整體晶片佈局面積為 0.5 mm2。
第三章為0.25-μm GaN/SiC HEMT製程應用於X頻段之連續J類功率放大器，透過連續J類的輸出匹配計算，從而調節基頻與二倍頻阻抗點，以達到寬頻高效率的效果。量測最大增益為24.0 dB，3-dB頻寬為 8.65-11.14 GHz，比例頻寬為24.9%，1-dB增益壓縮點之輸出功率約為 24.4 dBm，飽和輸出功率為 34.7 dBm，最大功率附加效率為 36.76 %。並於9.5 GHz下使用LTE 64 QAM，調變頻寬為5 MHz，於OP1dB量測，平均輸出功率為20.5 dBm，加入DPD後，整體相鄰通道比由28.7降至52.1，誤差向量幅度由3.26%降至0.35%。整體晶片佈局面積為 2.5 mm2，使用的為教育性晶片。
第四章為0.15-μm GaAs/SiC HEMT製程應用於Ku頻段E類電抗補償技術與級間匹配採用濾波器之寬頻功率放大器，希望輸出匹配透過E類放大器所延伸出的電抗補償技術拓展頻寬，順便達到E類放大器降低功率消耗的特點。並在級間匹配採用濾波器形式計算阻抗轉換，以減少平常因為級間窄頻匹配的缺陷，以及減少寄生效益帶來的壞處。操作頻率為10.65-17.22 GHz，增益為19.9 dB，比例頻寬為47.15%，飽和輸出功率為27.2 dBm，最大功率附加效率為31.47%，靜態功率消耗為785 mW。並於10 GHz下使用5G NR，調變頻寬為80 MHz，於OP1dB量測，平均輸出功率為17.5 dBm，加入DPD後，整體相鄰通道比由17.8降至28.1，誤差向量幅度由11.49%降至2.75%。整體晶片佈局面積為2 mm2，使用的為教育性晶片。
;This thesis focuses on high-efficiency broadband power amplifiers (PAs) in the X-band and Ku-band. The study employs 0.18-μm CMOS, 0.25-μm GaN/SiC HEMT, and 0.15-μm InGaAs pHEMT technologies to develop an X-band continuous-mode Class-F PA, an X-band continuous-mode Class-J PA, and a Ku-band broadband PA with reactance compensation in the output matching and a filter-based inter-stage matching network.
Chapter 2 presents an X-band PA using a 0.18-μm CMOS process. The output matching network is designed based on the continuous-mode Class-F approach to achieve a short circuit at the second harmonic and an open circuit at the third harmonic, thereby suppressing odd harmonics and improving efficiency. A stacked structure is implemented to enhance gain and output power. Measurement results show a maximum gain of 11.4 dB, a 3-dB bandwidth of 8.2-13.8 GHz with a fractional bandwidth of 26%, an output power of approximately 18.1 dBm at the 1-dB gain compression point, a saturated output power of 21.0 dBm, and a peak power-added efficiency (PAE) of 31.92%. LTE 16-QAM modulation with a 1.4 MHz bandwidth is tested at 9 GHz. At maximum measurable output power, the average output power reaches 18.7 dBm. After digital predistortion (DPD), the adjacent channel power ratio (ACPR) improves from 25.6 dB to 28.8 dB, and the error vector magnitude (EVM) decreases from 9.22% to 2.87%. The total chip layout area is 0.5 mm².
Chapter 3 discusses an X-band continuous-mode Class-J PA implemented using a 0.25-μm GaN/SiC HEMT process. The output matching network is designed based on continuous-mode Class-J principles, optimizing fundamental and second-harmonic impedances to achieve broadband high efficiency. Measurement results indicate a maximum gain of 24.0 dB, a 3-dB bandwidth of 8.65-11.14 GHz with a fractional bandwidth of 24.9%, an output power of approximately 24.4 dBm at the 1-dB gain compression point, a saturated output power of 34.7 dBm, and a peak PAE of 36.76%. LTE 64-QAM modulation with a 5 MHz bandwidth is tested at 9.5 GHz. At OP1dB measurement, the average output power is 20.5 dBm. With DPD applied, ACPR improves from 28.7 dB to 52.1 dB, and EVM reduces from 3.26% to 0.35%. The total chip layout area is 2.5 mm², and the chip is an educational chip.
Chapter 4 explores a Ku-band broadband PA using a 0.15-μm GaAs/SiC HEMT process, incorporating E-mode reactance compensation and filter-based inter-stage matching. The output matching network leverages reactance compensation derived from Class-E amplifiers to extend bandwidth while maintaining the power-saving characteristics of Class-E operation. The inter-stage matching network employs a filter-based impedance transformation to mitigate the drawbacks of narrowband inter-stage matching and reduce the negative effects of parasitic elements. The amplifier operates over 10.65-17.22 GHz with a gain of 19.9 dB and a fractional bandwidth of 47.15%. The saturated output power is 27.2 dBm, and the peak PAE is 31.47%, with a quiescent power consumption of 785 mW. 5G NR modulation with an 80 MHz bandwidth is tested at 10 GHz. At OP1dB measurement, the average output power is 17.5 dBm. With DPD applied, ACPR improves from 17.8 dB to 28.1 dB, and EVM decreases from 11.49% to 2.75%. The total chip layout area is 2 mm², and the chip is an educational chip. |
