| 摘要: | 本論文主要研究高功率、高效率四相位壓控振盪器及具有自動頻率校準技術之使用開關電容陣列寬頻本地振盪源。第二章的內容為操作在 K 頻段的四相位壓控振盪器，透過放大器交互耦接來實現高輸出功率及低相位雜訊。第三章則是介紹操作在 K 頻段及 Ka 頻段且使用 5 位元開關電容陣列之寬頻鎖相迴路設計。第四章首先介紹到頻率自動校準迴路，並透過實際整合進驗證過之寬頻鎖相迴路，來實現電路的頻段自適應追蹤技術。
第二章為使用電容耦合技術實現之四相位 E 類功率振盪器。首先會先設計出一 E 類功率放大器再透過交互耦接滿足振盪條件。透過由功率放大器回授形成的功率振盪器設計，本次設計的振盪器輸出功率及效率皆比傳統的交互耦合對要大得多， E 類匹配網路的設計透過 E 類負載公式以及負載遷移(Load pull)技術去最大化輸出功率和效率。在四相位部分，會先介紹電容耦合技術。最後利用電容耦合技術將兩個差動輸出的振盪器進行四相位耦合。本章節以台積電 0.18 μm CMOS 實現，再操作頻段內最大輸出功率約為 15 dBm，距離載波偏移 1 MHz 的相位雜訊為 -112.2 dBc/Hz，最小的相位誤差以及振幅誤差分別是 0.1°和 0.2 dB，優化指數 FOMQ達到−207.7。
第三章為操作在 K/Ka 頻段使用開關電容陣列之 5 位元鎖相迴路。前半部分會先介紹鎖相迴路的各個子電路及其設計過程，並且使用轉移函數來分析迴路的穩定性、抖動和迴路頻寬等系統模擬。此電路使用台積電 90 nm CMOS 製程實現，可調頻率範圍為 22.9 ~ 29.6 GHz (25.5%)，整體輸出功率為 -7 ~ -10 dBm，距載波偏移 1 MHz 相位雜訊在-93 ~ -103.5 dBc/Hz，最低抖動量為 138 fs。晶片面積為 1 × 1.34 mm2。
第四章首先會介紹自動頻率校準迴路。並要聚焦於講述閉迴路自動頻率校準(C-AFC)電路且詳細介紹所使用到的數位子電路。最後透過所設計之頻率校準迴路於晶片內整合已經驗證過的鎖相迴路，以此滿足電路能夠在兩位元開關電容陣列中自動校準。接著會介紹開迴路自動頻率校準技術(O-AFC)，並且優化前半部分使用到的搜尋法。透過整合第三章提出之 5 位元寬頻鎖相迴路，來實現快速的校準及鎖定。本章節透過兩種電路的分析與比較，藉此能夠更了解電路的優缺點，並以此能更快速地去對電路做選擇及設計。
;This paper explores the realization of a millimetre-wave local-oscillator (LO) chain that combines a high-power, high-efficiency quadrature voltage-controlled oscillator (QVCO) with a wide-tuning, multi-bit switched-capacitor-array (SCA) phase-locked loop (PLL) equipped with automatic frequency-calibration (AFC) circuitry. The work targets K- and Ka-band transceivers and emphasises techniques that raise RF output power, reduce phase noise, and enable rapid, digitally assisted frequency adaptation.
Chapter 2 details the conception and verification of a K-band QVCO that leverages a class-E load network to elevate both RF output power and DC-to-RF conversion efficiency. Two class-E power-amplifier cores are first optimised through load-pull simulations and E-class design equations; they are then cross-coupled and capacitively linked to generate precise quadrature outputs (0°, 90°, 180°, 270°) while satisfying the Barkhausen criterion. Fabricated in 0.18 µm TSMC CMOS, the oscillator covers 22.6 GHz to 23 GHz, delivers up to 15 dBm, and achieves −112.2 dBc/Hz phase noise at a 1 MHz offset. Measured phase- and amplitude-balance errors are only 0.1° and 0.2 dB, respectively, yielding a quadrature figure-of-merit FOMQ of −207.7 dBc/Hz within an active area of 0.797 mm².
Chapter 3 shifts focus to a 5-bit SCA-PLL that spans the K/Ka bands. The chapter first analyses how the SCA simultaneously realises a 25.5 % tuning range (22.9 GHz – 29.6 GHz) and a reduced KVCO, thereby enhancing phase-noise immunity and loop stability. Implemented in a 90 nm CMOS technology, the PLL produces −10 dBm to −7 dBm output power and attains −103.5 dBc/Hz to −93 dBc/Hz phase noise at a 1 MHz offset with 138 fs rms integrated jitter. A comprehensive transfer-function analysis verifies loop bandwidth, stability margin, and spur suppression, while circuit-level design considerations for the PFD, charge pump, loop filter, ILFD, and VCO are discussed in detail. The complete chip occupies 1.00 mm × 1.34 mm.
Chapter 4 examines two AFC topologies that address the challenges of wide-band, multi-bit calibration. A closed-loop AFC (C-AFC) is first embedded in a quadrature PLL using a 2-bit SCA, where a frequency-error detector and digital filter autonomously select the correct frequency band, enabling the loop to track process-voltage-temperature variations without degrading phase noise. An open-loop AFC (O-AFC) with an optimised search algorithm is then integrated with the 5-bit wide-band PLL of Chapter 3, providing rapid coarse-band selection followed by fine locking. Both AFC schemes are realised in 0.18 µm CMOS and evaluated side by side, clarifying their respective lock-time, phase-noise, and hardware-complexity trade-offs and furnishing practical design guidelines for future frequency-adaptive, multi-bit LOs in K- and Ka-band transceiver applications |
