| 摘要: | 隨著筆記型電腦的功能持續增強以及無線技術的普及，內部高頻電子元件與通訊模
組間的電磁干擾（Electromagnetic Interference, EMI）問題逐漸受到廣泛關注。尤其在DDR
記憶體、SSD儲存裝置等高速數據傳輸介面與Wi-Fi天線共存的情境下，內部產生的電
磁雜訊可能顯著影響無線通訊性能，導致通訊效率降低甚至訊號中斷。然而，目前針對
DDR 或 SSD 所產生雜訊對天線性能影響的研究仍然相對有限，且缺乏系統化的雜訊源
建模及干擾評估方法。
針對此問題，本論文以平台雜訊（platform noise）對 Wi-Fi天線的干擾為研究主軸，
提出一套整合理論、模擬與量測的分析流程。首先透過理論功率譜密度描述DDR訊號的
頻域特性，結合HFSS模擬取得DDR至天線間的轉移函數（transfer function），估算DDR
對天線造成的干擾強度，並與實際使用頻譜分析儀量測所得的結果進行比較。結果顯示，
模擬所預測的platform noise水平與實測值誤差約在5 dB內。
此外，透過Zero Span Mode的時域觀察可發現DDR在特定燒機條件下會產生週期
性活動，呈現1秒週期、50% duty cycle的行為。本研究亦透過燒機控制與探棒掃描確認
此一結論，並觀察到3D workload 雖不會產生強烈突發，但會造成連續性的背景雜訊升
高，進一步抬高platform noise底噪。
本論文所建立的建模與驗證方法不僅能有效預測內部子系統對平台雜訊的貢獻，亦
可作為系統早期設計階段的干擾評估工具，有助於降低系統整體EMI風險，提升無線通
訊穩定性，並減少後期以遮罩、吸波材等被動手段進行修正所需付出的額外成本與設計
代價。;With the increasing functionality of modern laptops and the widespread adoption of
wireless technologies, electromagnetic interference (EMI) between internal high-speed
electronic components and communication modules has become a growing concern. In
particular, the coexistence of high-speed data interfaces such as DDR memory and SSD storage
with Wi-Fi antennas can generate internal electromagnetic noise that significantly degrades
wireless communication performance, potentially resulting in reduced throughput or even
connection loss. However, current studies on the impact of noise from DDR or SSD components
on antenna performance remain limited, and a systematic approach to noise source modeling and
interference evaluation is still lacking.
To address this issue, this thesis focuses on the impact of platform noise on Wi-Fi antennas
and proposes an integrated methodology combining theoretical analysis, electromagnetic
simulation, and experimental measurement. Theoretical power spectral density (PSD) is first
used to characterize the frequency-domain behavior of DDR signals. This is followed by HFSS
based simulation to extract the transfer function from the DDR subsystem to the antenna,
enabling an estimation of DDR-induced interference. The simulated results are then compared
with actual measurements obtained using a spectrum analyzer, and the platform noise level
predicted by simulation was found to be within 5 dB of the measured values.
Furthermore, time-domain measurements using zero span mode reveal that under certain
burn-in conditions, DDR exhibits periodic burst activity with a 1-second cycle and approximately 50% duty cycle. This pattern was confirmed through controlled burn-in
experiments and near-field probing. In contrast, 3D workloads do not induce strong bursts but
instead elevate the continuous background noise level, effectively raising the overall platform
noise floor.
The modeling and validation methodology established in this thesis effectively predicts the
contribution of internal subsystems to overall platform noise. It also serves as a practical EMI
assessment tool in the early stages of system design, helping reduce EMI risks, improve wireless
communication reliability, and minimize the cost and design burden associated with late-stage
fixes such as additional shielding or absorber placement. |
