本論文在IEEE 802.3bz™-2016 規範下模擬乙太網路受射頻干擾（Radio Frequency Interference, RFI）的影響並提出解決方案。在受射頻干擾的影響下會造成訊號傳輸的失真，導致接收端等化器無法正確地還原出真實的傳送訊號，因此需要數位射頻干擾消除器(Digital Radio Frequency Interference Canceller)對射頻干擾進行消除，並且在此解決方案中考慮等化器的效應後並改良了所使用的演算法。 本論文所提方案為使用頻域自適應線性增強器(Adaptive Line Enhance, ALE)與基於自適應演算法的射頻干擾消除器，通過頻域估算 RFI 並加以扣除，以恢復訊號完整性。本研究在演算法的部分使用最小均方根演算法(Least Mean Square, LMS)進行改良，並針對功能改進硬體架構，並在模擬階段使用三種不同的通道搭配數種射頻干擾的頻段進行，分析方案在不同環境下的性能表現，而模擬結果顯示，不論是在十二米、六十五米或一百四十米的通道環境中，使用我們所提出的數位射頻干擾消除器消除射頻干擾後的訊號皆可使等化器正確收斂，且符合規範中所要求的位錯誤率(BER)。 而在硬體實現方面，本研究完成了基於自適應線性增強器之射頻干擾消除器的硬體設計。並先以verilog HDL語言進行功能描述與模擬，再透過晶片設計工具Design Complier進行合成及IC Complier在TSMC-40nm製程下完成佈局與驗證其電路功能。 關鍵字 : 自適應線性增強器、數位射頻干擾消除器、等化器 ;This thesis investigates the impact of Radio Frequency Interference (RFI) on Ethernet systems under the IEEE 802.3bz™-2016 standard and proposes a mitigation solution. RFI distorts transmitted signals, leading to incorrect recovery at the receiver. To address this, a Digital Radio Frequency Interference Canceller is employed to suppress interference. The proposed solution considers the effect of the equalizer and improves the employed algorithm accordingly. The method adopts a frequency-domain Adaptive Line Enhancer (ALE) combined with an adaptive algorithm-based RFI canceller. RFI is estimated and subtracted in the frequency domain to restore signal integrity. An enhanced Least Mean Square (LMS) algorithm is used to improve suppression performance. The hardware architecture is also refined for functional improvement. Simulations are conducted using three transmission channel lengths and various RFI bands to evaluate performance. Results show that, under 12-meter, 65-meter, and 140-meter channels, the proposed canceller effectively suppresses interference and enables proper equalizer convergence, achieving bit error rates (BER) compliant with standard specifications. For hardware implementation, the RFI canceller is designed based on the adaptive line enhancer. The system is described and simulated using Verilog HDL, synthesized with Design Compiler, and finalized with layout and verification using IC Compiler under the TSMC 40nm CMOS process.\ Keywords : Adaptive Line Enhancer , Digital RFI canceller , Equalizer
