隨著車用電子與自動駕駛技術的快速演進，車輛對於高速、穩定且即時之資料傳輸需求日益增加，相關的乙太網路技術因此逐漸被應用於車載通訊系統之中。在 IEEE 802.3bp™-2016（1000BASE-T1）標準中，採用單一雙絞線進行全雙工資料傳輸，其優勢在於節省線材、降低重量及成本等方面，惟仍面臨迴音干擾的問題。基於迴音通道響應的主成分集中在最前段，因此能以最低成本的類比迴音消除器置於ADC之前，先行消除掉其最大數值，以降低後續數位電路的複雜度。 基於IEEE 802.3bp™-2016 標準，本論文探討及實現了迴音消除器之類比有限脈衝響應濾波器電路設計，核心電路包含前級的類比暫存器(Tapped Delay Line)及後級的類比乘法器，其中類比暫存器藉由取樣保持(Sample and Hold)電路和旋轉開關陣列(Rotating Switch Array)使得暫存資料的排列為FIFO的形式，以提供後級數個類比乘法器的資料輸入，而類比乘法器採用的是四相位全差動的設計，實現暫存資料與演算法係數的乘積功能。最終利用共用輸出級的方式將各乘積進行加總，以產生輸入資料與演算法係數的卷積(Convolution)輸出，實現迴音消除器中類比有限脈衝響應濾波器的功能。 本論文採用TSMC 40nm製程，電路的操作頻率為375MHz，核心電壓為0.9V，電路的誤差值經由代入系統模擬中得到功能驗證，在不同的網路線長度下，皆能消除迴音通道響應中的最大數值。 ;With the rapid advancement of automotive electronics and autonomous driving technologies, the demand for high-speed, stable, and real-time data transmission in vehicles is increasing. Ethernet technologies are thus being gradually integrated into in-vehicle communication systems. The IEEE 802.3bp™-2016 (1000BASE-T1) standard employs a single twisted pair to achieve full-duplex transmission, offering advantages such as reduced cabling, lower weight, and cost savings. However, echo interference remains a critical challenge. Since the dominant components of the echo channel response are concentrated at the beginning, a cost-effective analog echo canceller can be placed before the ADC to suppress major interference in advance, thereby reducing the complexity of subsequent digital circuitry.This thesis presents an analog finite impulse response (FIR) filter circuit based on the IEEE 802.3bp™-2016 standard. The core architecture consists of a front-end analog tapped delay line and a back-end analog multiplier array. The analog delay line is realized using sample-and-hold circuits and a rotating switch array to form a FIFO data sequence, which feeds multiple analog multipliers. The multipliers employ a four-phase fully differential design to compute the product between input data and algorithm coefficients. The resulting products are summed using a shared output stage to perform convolution, thus realizing the analog FIR filtering function required for echo cancellation.The chip is implemented using the TSMC 40nm CMOS process, operating at 375 MHz with a core voltage of 0.9V. System-level simulations validate the error performance of the circuit, demonstrating effective suppression of the dominant echo components under various cable length conditions.
