結合P型摻雜層與超級接面結構之碳化矽平面型分離閘極金氧半場效電晶體模擬分析;Simulation Analysis of Planar Split-gate SiC MOSFETs Incorporating a P-type Doping Layer and Superjunction Structure

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Title:	結合P型摻雜層與超級接面結構之碳化矽平面型分離閘極金氧半場效電晶體模擬分析;Simulation Analysis of Planar Split-gate SiC MOSFETs Incorporating a P-type Doping Layer and Superjunction Structure
Authors:	黄駿升;Huang, Jun-Sheng
Contributors:	電機工程學系
Keywords:	碳化矽;金氧半場效電晶體;分離閘極;超級接面;SiC;MOSFET;Split-gate;Superjunction
Date:	2025-08-25
Issue Date:	2025-10-17 12:56:46 (UTC+8)
Publisher:	國立中央大學
Abstract:	本文利用Silvaco TCAD模擬軟體在碳化矽分離閘極金氧半場效電晶體 (SGMOSFET)中加入P型摻雜層以及超級接面結構，目標為建構出碳化矽分離閘極超級接面金氧半場效電晶體 (split-gate superjunction central-implanted MOSFET, SGSJCIMOSFET)，P型摻雜層的加入目的為降低氧化層峰值電場以及降低反向傳輸電容值，而加入超級接面結構的目的為在降低元件的特徵導通電阻值的同時，提升元件的崩潰電壓，並且透過兩者的搭配提升元件的BFOM及HF-FOM特性表現。研究中首先對傳統碳化矽金氧半場效電晶體 (VDMOSFET)，調整其JFET區寬度及摻雜濃度進行分析，接著依序於VDMOSFET中加入分離閘極結構建構出SGMOSFET，包含改變閘極長度及觀察電性變化，最後在SGMOSFET加入P型摻雜層以建立出SGCIMOSFET，並且調整其寬度以便進行探討。為了討論結構差異造成的影響，後續比較了三種元件的電氣特性，雖然SGCIMOSFET的特徵導通電阻值為三者中最高，不過卻兼具最高的崩潰電壓值、最低的反向轉移電容值以及最低的氧化層峰值電場值。同時也利用了Silvaco混合模式功能將三種元件匯入建立好的雙脈衝測試平台，模擬了動態特性表現，SGCIMOSFET展現出了最低的切換時間、開關損耗以及閘極電荷特性。後續於VDMOSFET、SGMOSFET以及SGCIMOSFET中各自加入超級接面結構，建立出SJMOSFET、SGSJMOSFET以及SGCISJMOSFET，為了使電氣特性達到最佳，各自針對不同的電荷平衡條件下進行分析。參數最佳化後，三者的特徵導通電阻值以及崩潰電壓值差異很小，不過SGCISJMOSFET展現出了最低的反向轉移電容值以及最低的氧化層峰值電場值，接著也在雙脈衝測試平台模擬了元件的動態特性表現，SGCISJMOSFET展現出了最低的切換時間、開關損耗以及閘極電荷特性。最後，也分析了有無超級接面結構對SGCIMOSFET造成的電氣特性差異，比較了SGCIMOSFET與SGCISJMOSFET，超級接面結構的加入使得後者在的崩潰電壓增加的同時也充分降低了特徵導通電阻值。在汲極電壓升高時下也幫助空乏區快速夾擠，使反向轉移電容降的更低，並且兩元件的氧化層峰值電場值沒有太大差異，顯示超級接面結構不會使閘極可靠性變得更差。最後在雙脈衝平台模擬的結果中，SGCISJMOSFET表現出較低的開關損耗特性。 ;In this study, Silvaco TCAD is utilized to introduce a P-type doped layer and a superjunction structure into SiC split-gate MOSFET (SGMOSFET), aiming to develop a SiC split-gate superjunction central-implanted MOSFET (SGSJCIMOSFET). The P-type doped layer is introduced to suppress the maximum oxide electric field and reduce the reverse transfer capacitance. Meanwhile, the SJ structure is implemented to simultaneously increase the breakdown voltage and decrease the specific on-resistance. By combining these two structural enhancements, the device achieves improved performance in both BFOM and HF-FOM. First, optimization and analysis were conducted on a conventional SiC VDMOSFET by adjusting the width and doping concentration of its JFET region. Subsequently, a split-gate structure was introduced into VDMOSFET to construct SGMOSFET, including modifications to the gate length and investigation of the resulting electrical characteristics. Finally, a P-type doped layer was added to SGMOSFET to develop SGCIMOSFET, with further analysis conducted by adjusting its width. To investigate the effects of structural differences, the electrical characteristics of the three devices were compared. Although SGCIMOSFET exhibited the highest specific on-resistance, it also demonstrated the highest breakdown voltage, the lowest reverse transfer capacitance, and the lowest maximum oxide electric field. In addition, Silvaco′s mixed-mode simulation was used to import three devices into double-pulse test (DPT) platform to evaluate their dynamic performance. SGCIMOSFET showed the shortest switching time, the lowest switching loss, and the smallest gate charge. Subsequently, superjunction structures are integrated into VDMOSFET, SGMOSFET, and SGCIMOSFET to construct SJMOSFET, SGSJMOSFET, and SGCISJMOSFET, respectively. Each device is analyzed under various charge-balance conditions to optimize. After parameter optimization, the specific on-resistance and breakdown voltage of the three devices show only minor differences. However, SGCISJMOSFET demonstrates the lowest reverse transfer capacitance and the lowest maximum oxide electric field. The dynamic characteristics of all three devices were evaluated using DPT platform, where SGCISJMOSFET exhibited superior switching performance, the shortest switching time,and lowest switching loss and gate charge. Finally, the influence of the superjunction structure on SGCIMOSFET is further investigated by comparing SGCIMOSFET and SGCISJMOSFET. The addition of the superjunction structure significantly increases the breakdown voltage while simultaneously reducing the specific on-resistance. Under high drain voltage conditions, it promotes quickly expansion of the depletion region, leading to a further reduction in reverse transfer capacitance. Moreover, the maximum oxide electric fields in both structures remain comparable, indicating that the gate reliability is not compromised. SGCISJMOSFET also demonstrates improved switching loss characteristics, as confirmed through DPT simulation.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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