支援複合點數無衝突定址之快速傅立葉轉換架構;A Conflict-Free Memory Addressing Scheme for Fast Fourier Transform (FFT) Architecture Supporting Composite FFT Sizes

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Title:	支援複合點數無衝突定址之快速傅立葉轉換架構;A Conflict-Free Memory Addressing Scheme for Fast Fourier Transform (FFT) Architecture Supporting Composite FFT Sizes
Authors:	張致嘉;Chang, Chih-Chia
Contributors:	電機工程學系
Keywords:	無衝突定址;記憶體快速傅立葉轉換;原地讀取策略;混合基底快速傅立葉轉換處理器
Date:	2025-08-26
Issue Date:	2025-10-17 12:56:58 (UTC+8)
Publisher:	國立中央大學
Abstract:	為因應現代數位訊號處理系統日益多樣且彈性的運算需求，支援組合式點數計算之可配置型快速傅立葉轉換(Fast Fourier Transform, FFT)處理器日漸普及。本論文提出一種基於記憶體的連續流(Continuous-Flow Memory-Based)快速傅立葉轉換架構，可支援從32點至4096點共63種不同點數之快速傅立葉轉換運算模式，以滿足各類應用對於多點數支援的需求。為有效降低輸入緩衝區、中間儲存與輸出重排所需的記憶體數量與總容量，本文提出一套具無衝突(Conflict-Free)且原地(In-Place)特性的位址配置方法。計算核心部分利用多路徑延遲交換器(Multi-Path Delay Commutator)架構設計，具備最多五條平行處理路徑，並支援多種基數的蝴蝶運算(Butterfly Operation)，包括radix-3、radix-4、radix-5、radix-(4·2)、radix-3²與radix-4²，以提升在複合點數組合下的計算效率與硬體彈性。此外，本文引入三元組多基數(3-tuple multi-radix)位址表示法，用於虛擬位址產生，進一步將僅適用於傳統2的冪次點數設計的無衝突位址與記憶體配置機制概念擴展至更廣泛的非2的冪次情況。在此設計下，整體快速傅立葉轉換架構僅需2N個Word的記憶體，且最多僅需使用P_max個記憶體區塊。根據實作於TSMC 28nm製程的綜合結果顯示，所提出之快速傅立葉轉換處理器架構可達最高操作頻率500M Hz，在1200點快速傅立葉轉換下，其Power為58.4(mW)，在正規化後之單位面積吞吐量方面，於1200點與4096點快速傅立葉轉換模式下分別達成2088.50(MS/s/mm^2)和2750.20(MS/s/mm^2)的結果。與其他參考文獻相比，本設計在執行非 2 的冪次點數快速傅立葉轉換時，於單位面積下所能處理的吞吐量具備相當突出的效能。;To address the increasing diversity and flexibility requirements of modern digital signal processing systems, configurable Fast Fourier Transform (FFT) processors that support composite power point sizes have become increasingly prevalent. This paper presents a continuous-flow memory-based FFT architecture capable of supporting 63 FFT modes ranging from 32-point to 4096-point operations, thereby meeting the demands of various multi-point applications. To effectively reduce the number and total size of memory blocks needed for input buffering, intermediate storage, and output reordering, a conflict-free and in-place strategy is proposed. The processing element adopts a Multi-Path Delay Commutator (MDC) architecture which can work with up to five parallel processing paths. It supports multiple radix butterfly operations, including radix-3, radix-4, radix-5, radix-(4·2), radix-3², and radix-4². This makes the system more efficient and flexible when working with composite point sizes. Furthermore, a 3-tuple multi-radix address representation is introduced for virtual address generation, which extends the conventional conflict-free and in-place memory mapping scheme—originally limited to power-of-two FFT sizes—to a broader set of non-power-of-two configurations. Under this design, the entire FFT architecture requires only 2N-word of memory and at most Pmax memory banks. Synthesis results in TSMC 28nm process demonstrate that the proposed FFT processor architecture achieves a maximum operating frequency of 500 M Hz. For a 1200-point FFT, the power consumption is 58.4 mW. After normalization, the throughput per unit area reaches 2088.50 (MS/s/mm²) for 1200-point FFTs and 2750.20 (MS/s/mm²) for 4096-point FFTs. Compared with prior works, the proposed design demonstrates excellent performance in terms of the normalized throughput per area for non-power-of-two FFT sizes.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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