用於混合式波束成形正交分頻多工系統之高維度通道張量估測演算法之硬體架構設計與實作;Hardware Design for Higher-Order Tensor-Based Channel Estimation in Hybrid Beamforming MIMO-OFDM Systems

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/98579

Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/98579

Title:	用於混合式波束成形正交分頻多工系統之高維度通道張量估測演算法之硬體架構設計與實作;Hardware Design for Higher-Order Tensor-Based Channel Estimation in Hybrid Beamforming MIMO-OFDM Systems
Authors:	林采陞;Lin, Cai-Sheng
Contributors:	電機工程學系
Keywords:	正交分頻多工;張量;正交匹配追蹤;通道估測;混合式波束成形;硬體設計;orthogonal frequency-division multiplexing;tensor;orthogonal matching pursuit;channel estimation;hybrid beamforming;hardware design
Date:	2025-08-26
Issue Date:	2025-10-17 12:57:02 (UTC+8)
Publisher:	國立中央大學
Abstract:	本研究主要針對旋轉張量正交匹配追蹤(Tensor-Orthogonal Matching Pursuit with Rotation, T-OMP-R)演算法與干擾消除演算法(Interference cancellation, IC)兩種演算法設計相應的硬體架構，並比較多種架構對於估測準確度、電路面積、執行時間的綜合效率。此演算法是一種基於高維張量與壓縮感知(compressive sensing, CS)的通道估測演算法，應用在混合式波束成形(hybrid beamforming)正交分頻多工(orthogonal frequency-division multiplexing, OFDM)系統。論文中使用的系統模型為單使用者多輸入多輸出(multi-input multi-output, MIMO)，並在接收端跟傳送端都採用均勻矩形天線陣列(uniform rectangular array, URA)，加上路徑延遲，以此構造出共五個維度的通道張量模型，其維度大小與龐大的數據量使得計算的複雜度非常高，對於通道估測這種實時性要求高的應用形成挑戰，因此本研究首先對演算法本身進行複雜度優化，對計算複雜度最高的首個搜尋維度使用階層式搜尋、裁減搜尋空間，以及透過重構、化簡演算法公式等方式，在不影響到估計準確度的合理範圍，大幅減少所需的計算次數。除了演算法的優化，本研究著重評估不同演算法階段需要用到的硬體種類，並採用模組化與硬體資源共享的策略以提高使用效率，並進行資料路徑最佳化以減少關鍵路徑延遲，在記憶體方面，我們也根據存取資料的特性進行不同存取方式的討論，以配合運算單元的吞吐率。本研究提出的可變精度乘加處理器，相比全高精度的乘加器陣列，可以節省27%的乘法器面積、38%的記憶體面積，根據實作結果，本電路設計在28奈米製程的條件下，擁有合理的執行時間、估測準確度，具有良好的實作可行性。;This study focuses on the hardware architecture design of the channel estimation and sensing algorithm in hybrid beamforming multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) systems using uniform rectangular antenna arrays. The algorithms are based on high-dimensional tensors and compressive sensing (CS). The large dimensionality and massive data result in extremely high computational complexity, which poses challenges for real-time channel estimation applications. Therefore, multiple architectures in terms of estimation accuracy, circuit area, and execution time are evaluated during design phase. We first optimize the computation complexity by applying a hierarchical search, reducing the search space in the first and most complex search dimension, and simplifying algorithmic expressions through reformulation. These strategies significantly reduce computational requirements without compromising estimation accuracy. In addition to algorithmic optimization, this study evaluates the types of hardware needed at different algorithmic stages. A modular and hardware resource-sharing approach is adopted to improve efficiency, along with optimized data paths to minimize critical path delays. For memory access, different strategies are discussed based on data access characteristics to avoid slowing down execution. The proposed variable-precision multiplication and addition processor (MAP) can save 27% of multiplier area and 38% of memory area compared to a high-precision MAP. Implementation results show that the proposed circuit design, under the TSMC 28nm process, achieves reasonable execution time and estimation accuracy.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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