基於SRAM的記憶體內運算之測試;Testing of SRAM-based Computing-In Memories

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Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/98608

Title:	基於SRAM的記憶體內運算之測試;Testing of SRAM-based Computing-In Memories
Authors:	李耿嘉;Li, Geng-Jia
Contributors:	電機工程學系
Keywords:	靜態隨機存取記憶體;記憶體內運算;記憶體測試;SRAM;Computing-in-Memory;Digital CIM;Memory Testing
Date:	2025-08-27
Issue Date:	2025-10-17 12:59:50 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著資料密集型應用的持續增長，傳統馮‧諾伊曼架構所固有的「記憶體牆問題」已成為系統效能的一大瓶頸。為了解決此問題，記憶體內運算(Computing-In-Memory, CIM)架構應運而生，使得運算能直接在記憶體陣列中執行，從而降低資料搬移所造成的延遲與功耗。CIM架構可大致分為數位CIM(Digital CIM, DCIM)與類比CIM(Analog CIM, ACIM)，而兩者皆帶來不同的測試挑戰。在本論文中，我們提出一套自動化的DCIM故障建模流程。此流程以簡化後的DCIM設計為輸入，透過系統性的缺陷注入來產生對應的Spice網表，並同時生成完整的功能操作序列以供模擬使用。為達成此目標，我們提出兩項關鍵技術：其一是基於狀態轉換圖的操作序列生成方法，能系統化地涵蓋所有可能的操作；其二是DCIM單元的對稱性檢查機制，可有效減少缺陷注入數量並縮短模擬時間。除此之外，我們亦設計了一個二階段缺陷尺寸搜尋技術，以找出缺陷範圍及其對應的故障行為。為驗證所提方法的有效性，我們以具代表性的DCIM設計進行實驗，並透過模擬結果分析歸納出多種DCIM特有的故障行為。最後，根據這些行為，我們定義了DCIM特有的故障模型，並進一步設計測試演算法，以完整覆蓋所定義之故障。;As data-intensive applications continue to grow, the memory wall problem inherent in traditional Von Neumann architectures has become a critical bottleneck for system performance. To address this issue, Computing-In-Memory (CIM) architectures have emerged, allowing computations to be performed directly within memory arrays, thereby reducing data movement latency and power consumption. CIM architectures can be broadly categorized into Digital CIM (DCIM) and Analog CIM (ACIM), each introducing distinct testing challenges. In this thesis, we propose an automated fault modeling flow for DCIMs. The automated fault modeling flow that takes a reduced DCIM design as input, systematically executes fault injection and generates corresponding Spice netlist, and generates comprehensive functional operation sequences for simulation. A state transition diagram-based method is proposed to generate comprehensive functional operation sequences. A symmetric property checking method for a DCIM cell is proposed to reduce the number of defect injection such that the simulation time can be reduced. Also, a simple two-stage defect size search technique is proposed to find the defect range and the corresponding fault behavior. A representative DCIM design is used to validate the proposed automated fault modeling flow and demonstrate its effectiveness. In addition, we analyze the simulation results from this design to identify DCIM-specific fault behaviors. Based on these behaviors, we define corresponding fault models for the DCIM and develop test algorithms to cover the defined faults.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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