具有高可靠度之通道擊穿型28nm 2kb 雙電晶體單次編程記憶體晶片;Design and Development of a High-Reliability 28nm 2kb 2-transistors One Time Programming Memory chip with Channel-Avalanche Programming

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Title:	具有高可靠度之通道擊穿型28nm 2kb 雙電晶體單次編程記憶體晶片;Design and Development of a High-Reliability 28nm 2kb 2-transistors One Time Programming Memory chip with Channel-Avalanche Programming
Authors:	侯佩君;Hou, Pei-Jyun
Contributors:	電機工程學系
Keywords:	一次性可編程記憶體矩陣;嵌入式記憶體;雪崩崩潰;One-time programmable memory;embedded memory;avalanche breakdown
Date:	2025-09-22
Issue Date:	2025-10-17 13:00:54 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著智慧裝置、物聯網和人工智慧的快速發展，儲存運算資料量的增加對於高密度記憶體的需求更是大幅上升，其中資料存取的安全性和可靠度尤其重要，因此斷電後能繼續保存資料的非揮發性記憶體 (Non-Volatile Memory, NVM) 成為嵌入式系統與安全應用的關鍵技術，包含了可變電阻式記憶體(Resistive Random-Access, RRAM)、快閃記憶體 (FLASH Memory)，以及一次性可編程記憶體 (One Time Programmable Memory, OTP) 等記憶體。本研究提出記憶單元面積僅0.152μm2的2T OTP架構，其中1T作為控制電晶體，另外1T則作為儲存電晶體使用，於儲存位元的閘極端使用浮接 (floating) 設計，實現相同於source(n+)/ channel(p)/ drain(n+) 的二極體作用，本架構所採用的編程機制為雪崩擊穿 (Avalanche Breakdown) ，透過施加的drain-source電壓(VDS)加大，使drain/channel接面處內建電場增強，並加速少數載子獲得高動能，這些高能載子引發碰撞游擊效應 (Impact Ionization) ，產生電子-電動對 (electron-hole pair, EHP) 並觸發雪崩擊穿，最終使drain-channel接面發生雪崩擊穿而受損，形成永久性斷路。本晶片設計容量為2kb的OTP記憶體矩陣，可完全兼容於28nm HKMG CMOS邏輯技術平台，不需要額外製程步驟，因此未來可持續微縮至3nm FinFET製程，整體矩陣的良率為96.875%，並且在攝氏150度下烘烤720小時後仍有良好的資料保存能力，在分別進行105次編程和104次讀取後，仍可以正常操作且具有足夠的讀取窗口供感測放大器進行0/1判斷。綜合而言，該2T OTP架構具有小面積、高度可靠性、高安全性和優秀的抗干擾能力等優勢，顯示其在嵌入式系統應用中具備良好潛力。;The rapid advancement of smart devices, the Internet of Things (IoT), and artificial intelligence (AI) has significantly increased the demand for high-density memory due to the growing volume of data storage and processing. Among various performance considerations, data security and reliability are of paramount importance. Consequently, non-volatile memory (NVM), which retains data without a continuous power supply, has emerged as a crucial technology for embedded systems and secure applications. Prominent examples include resistive random-access memory (RRAM), flash memory, and one-time programmable (OTP) memory. In this work, we propose a highly compact 2T OTP memory architecture with a unit cell area of only 0.152 μm2. In this architecture, one transistor (1T) serves as a control device, while the other with a floating gate functions as a storage transistor. This storage transistor can be conceptually modeled as a source (n+) / channel (p) / drain (n+) diode. The programming mechanism employed is avalanche breakdown. As the drain-to-source voltage (VDS) increases, the built-in electric field across the p-n junction is enhanced. This enhanced field accelerates minority carriers to high kinetic energies, which, in turn, initiate impact ionization. This process generates electron-hole pairs (EHPs) and further triggers avalanche breakdown. The avalanche breakdown permanently destroys the drain/channel junction, resulting in a permanently open circuit. The proposed chip integrates a 2kb memory array, which is fully compatible with 28nm high-k metal gate (HKMG) CMOS technology and requires no additional fabrication steps. This compatibility allows for further scaling to the 3nm FinFET technology node. The memory array demonstrates a high yield of 96.875% and exhibits excellent data retention after being baked at 150 °C for 720 hours. Furthermore, the chip remains fully functional and maintains a sufficient memory window for accurate 0/1 sensing by the sense amplifier (SA), even after 105 program operations and 104 read cycles in separate tests. In summary, the proposed 2T OTP architecture offers a number of advantages, including a small unit cell size, high reliability, enhanced security, and excellent data disturbance immunity, making it a promising candidate for embedded memory applications.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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