| 摘要: | 記憶體技術與運算需求近年快速成長，一方面追求更高的資料吞吐與更低的能耗，
另一方面也希望在晶片內直接取得可靠的亂數，做為安全與各式機率運算的共同基礎。
傳統以演算法產生的亂數(PRNG)雖易於使用，但受限於種子與可預測性；硬體亂數
(TRNG)可提供物理隨機性，卻常仰賴額外雜訊源與複雜類比路徑，導致面積與能耗不易
壓低、成本高。在這樣的背景下，如何以簡單、可調、可驗證的方式，讓亂數在記憶體
陣列內產生，成為值得關注的方向。電阻式隨機存取記憶體(RRAM)具備結構簡潔、面
積小、寫入快速與與製程相容性佳等特性，並且元件本身存在的自然波動與微小差異，
為隨機性提供了可利用的來源。若能把這些變化轉成品質優秀、可控制的位元，將可同
時滿足儲存與運算對亂數的即時需求，並降低系統搬移與能耗的負擔。
本研究以 40 nm 65 kb 1T1R RRAM 為平台，提出一個以雙記憶胞干擾為核心的機
率性輸出方法，搭配電流感測放大器將相鄰兩單元在低阻態操作下的微小變異轉換為解
耦距離，再進一步轉為機率位元(Probabilistic bit)。實驗首先藉由線性連續漸進式調變量
測方式分出清楚可分的多阻態分布，並完成讀取擾動、資料保存時間(150°C/672 小時)、
耐久度測試等可靠度量測。之後，以電流感測放大器連續讀取取得字串，測試漢明距離、
漢明權重、自相關函數與 NIST 等多項測試。結果顯示，所產生的 p-bits 在均勻性、獨
立性與時間相關性皆表現良好，且符合 NIST 測試標準。整體架構不需額外雜訊源與繁
雜的處理，可於記憶體陣列內直接利用微雜訊產生高品質的機率位元，具備易整合、低
成本、可擴充等優勢，適合應用於硬體安全、機率/隨機計算、記憶體內運算等應用領域，
並具備擴充到更大陣列與更高輸出速率的潛力。
;Rapid advancements in memory technology and computing demand have driven innovation
in recent years. There′s a dual imperative: to achieve higher data throughput with reduced
energy consumption and to generate reliable, on-chip randomness for security and
probabilistic computations. While software-based pseudo-random number generators
(PRNGs) are convenient, they′re limited by their dependence on seeds and predictability. In
contrast, hardware true random number generators (TRNGs) offer physical randomness
but often require additional noise sources and complex analog front-ends, increasing area,
power, and integration costs. This context highlights the critical need for a simple, tunable,
and verifiable method to generate randomness directly within the memory array.
Resistive random-access memory (RRAM) is a promising candidate for this purpose due to
its simple structure, small footprint, fast write speed, and process compatibility. Critically, its
inherent physical fluctuations and minor variations provide a valuable source of randomness.
If these variations can be reliably converted into high-quality, controllable bits, it could enable
on-demand randomness for both data storage and computation, thereby minimizing data
movement and energy overhead.
This work presents a novel approach utilizing a 40nm 65kb 1T1R RRAM platform to
generate probabilistic bits (p-bits) via a dual-cell interference method. A current sense
amplifier is used to continuously read a pair of adjacent cells in the low-resistance state. The
minute difference between their currents is then converted into a decoupled distance, which is
subsequently mapped to probabilistic bits. To establish stable operational windows, we first
employed a linear continual incremental tuning process to achieve well-separated, multilevel resistance distributions. We also conducted comprehensive reliability evaluations,
including read disturb, retention at 150 °C for 672 hours, and endurance tests. |
