| 摘要: | 隨著車用電子系統快速演進， 包含行車安全、自動駕駛輔助與即時 AI 影像處理等應用， 對於高效率數據傳輸的需求日益提升。為因應此趨勢，本論文依據 IEEE 802.3bp™-2016 標準，提出一套適用於車用乙太網路的數位基頻收發機架構。針對車載通訊環境中的挑戰，設計了專用數位濾波演算法與系統架構，實現通道等化、迴音消除與時序回復等核心模組之電路設計與整合。本篇設計採用改良後的低複雜度演算法、常模數演算法 (Constant Modulus Algorithm, CMA)、決策導向（Decision Directed,DD）技術進行通道等化，以有效對抗通道失真。等化器由前饋等化器（Feedforward Equalizer, FFE）與決策回饋等化器（Decision Feedback Equalizer, DFE）組成，前者負責抑制前符號間干擾，後者負責抑制後符號間干擾。在單一一對雙絞線雙向傳輸環境中，迴音干擾相當顯著，故需特別設計對應的迴音消除系統，本篇特別改良以往的迴音消除器，針對整個迴音響應，總共進行三次迴音消除以達到更佳的效果。為處理時脈漂移與取樣時機不一致問題，採用 Mueller and Muller 相位檢測法作為時序回復的核心技術。在硬體部分，電路以Verilog HDL撰寫與模擬，並利用 Xilinx FPGA進行驗證，最後以Synopsys Design Compiler與IC Compiler於TSMC 40nm製程下完成電路合成與晶片設計。
;With the rapid evolution of automotive electronic systems—encompassing applications such as driving safety, advanced driver-assistance systems (ADAS), and real-time AI-based image processing—the demand for high-efficiency data transmission has significantly increased. To address this trend, this thesis proposes a digital baseband transceiver architecture for automotive Ethernet, compliant with the IEEE 802.3bp™-2016 standard. In response to the challenges of in-vehicle communication environments, dedicated digital filtering algorithms and system architectures are designed and implemented, including the circuit design and integration of key modules such as channel equalization, echo cancellation, and timing recovery.
To effectively mitigate channel distortion, an enhanced low-complexity Decision-Directed (DD) algorithm is adopted for channel equalization. The equalizer consists of a Feedforward Equalizer (FFE) to suppress precursor inter-symbol interference and a Decision Feedback Equal- izer (DFE) to suppress postcursor interference. In a full-duplex transmission environment using a single twisted pair, echo interference becomes significant. Therefore, a customized echo can- cellation system is proposed, improving upon conventional designs by performing echo cancel- lation three times across the entire echo response to achieve enhanced suppression.
To resolve issues related to clock drift and sampling time mismatch, the Mueller and Muller phase detection algorithm is employed as the core timing recovery technique. The hardware is described and simulated using Verilog HDL, and verified on a Xilinx FPGA platform. Finally, logic synthesis and chip design are completed using Synopsys Design Compiler and IC Compiler with the TSMC 40nm CMOS process. |
