| 摘要: | 隨著無線通訊世代的演進與硬體技術的快速發展，無人載具（Unmanned Aerial
Vehicle, UAV）在監控、災害應變、物流運輸及臨時中繼通訊等應用中展現高度潛力。
特別是在5G 與未來6G 的發展背景下，UAV 在高頻（Ka-band）與寬頻場景下的通訊可
靠性需求日益提升。然而，由於UAV 的飛行高度與環境高度動態，其無線通道特性易
受多徑效應（Multipath Fading）與符號間干擾（Inter-Symbol Interference, ISI）影響，對
系統效能造成重大挑戰。為解決此問題，本論文依據3GPP TR 38.901 標準，建立了符
合Ka 頻段特性的模擬環境，並考慮TDL-A、TDL-B 與TDL-C 三種通道模型，模擬不
同延遲擴展與能量分佈下的效能表現。
在接收機架構方面，本研究提出並實現了一個基於決策回授等化器（Decision
Feedback Equalizer, DFE）的設計，包含前饋等化器（Feedforward Equalizer, FFE）與回
授等化器（Feedback Equalizer, FBE），分別對應消除pre-cursor 與post-cursor 之干擾。
在演算法上，考慮通道為緩慢時變通道（slow fading），通道在相干時間(τc) 內保持
不變，因此採用計算複雜度低、硬體實現簡單的Least Mean Square (LMS) 與其變體
sign-LMS 作為適應演算法，以達成通道估測與等化器權重更新。此外，本研究亦針
對64APSK 之軟性解調進行設計。利用64APSK 星座圖的象限對稱性，提出簡化LLR
（Log-Likelihood Ratio）計算的演算法，相較於傳統的Log-MAP 演算法完全省去了取對
數與指數的運算、減少了75% 的乘法運算與86% 的加減法運算，相較於Max-Log-MAP
驗算法則減少了62.5% 的乘法運算與60.6% 的加減法運算。
在硬體實現部分，本研究採用Transposed-form FIR 架構，以降低關鍵路徑延遲，並
透過Time sharing 技術將組合邏輯電路的使用量壓縮至理論值的12.5%，大幅減少面積
與功耗。在電路驗證階段，首先於SMIMS VeriEnterprise Xilinx FPGA 上進行功能驗證，
隨後以TSMC 40 nm 製程完成晶片實作，晶片最高操作頻率達384.6 MHz，優於規格需
求的320 MHz，證明該設計在效能與實用性上皆具備顯著優勢。;Unmanned aerial vehicles (UAVs) have recently attracted considerable attention in applications
such as surveillance, disaster response, logistics, and temporary relay communications.
With the advancement of 5G and the emerging 6G era, the demand for reliable communication
in Ka-band high-frequency and broadband scenarios has grown rapidly. However, UAV
channels are strongly influenced by multipath fading and inter-symbol interference (ISI) due to
dynamic flight altitudes and complex propagation environments, which significantly degrade
system performance.
To address these challenges, this thesis develops a simulation environment based on the
3GPP TR 38.901 standard, considering TDL channel models to evaluate system behavior under
different delay spreads and power distributions. A Decision Feedback Equalizer (DFE)
is designed and implemented, which consists of a Feedforward Equalizer (FFE) and a Feedback
Equalizer (FBE) to cancel pre-cursor and post-cursor interference, respectively. A lowcomplexity
Least Mean Square (LMS) algorithm and its variant sign-LMS are applied for adaptive
channel estimation and weight updating.
In addition, this thesis proposes a soft-output demodulation method for 64APSK modulation.
By exploiting constellation quadrant symmetry, the proposed approach simplifies log-likelihood
ratio (LLR) computation, effectively reducing complexity while supporting both hard and soft
decision decoding. For hardware realization, a Transposed-form FIR filter combined with a
time-sharing technique , significantly lowering chip area and power consumption. Functional
verification was implementation in TSMC 40-nm CMOS technology. The final chip achieves a
maximum operating frequency of 384.6 MHz, exceeding the target specification of 320 MHz,
thereby demonstrating both the efficiency and practicality of the proposed design. |
