使用120-nm GaN 與 100-nm GaAs pHEMT 製程之Q 頻段功率放大器與D頻段放大器;Q-band Power Ampli ers and D-band Ampli ers in 120-nm GaN and 100-nm GaAs pHEMT Technologies

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Title:	使用120-nm GaN 與 100-nm GaAs pHEMT 製程之Q 頻段功率放大器與D頻段放大器;Q-band Power Ampli ers and D-band Ampli ers in 120-nm GaN and 100-nm GaAs pHEMT Technologies
Authors:	陳柏叡;Chen, Po-Jui
Contributors:	電機工程學系
Keywords:	功率放大器;砷化鎵;Q頻段;D頻段;PA;GaN;GaAs;D-band
Date:	2026-01-19
Issue Date:	2026-03-06 19:00:24 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文聚焦於功率放大器的設計與討論，我們使用了穩茂所提供之WIN120-nm GaN on SiC HEMT 和 100-nm GaAs pHEMT 製程來實現各種不同架構的功率放大器，在第一章中我們闡述本論文研究動機與背景。在第二章，我們重新設計並使用WIN120-nmGaNonSiCHEMT 製程並操作於Q 頻段中心頻率40GHz之功率放大器。小訊號量測在操作頻率40GHz下增益可得7.98dB，而大訊號量測結果在操作頻率 40 GHz 下，OP1dB 為 21.6 dBm，在 P1dB 下的 PAE 為 10.8%。在第三章，我們設計一使用WIN100-nm GaAs pHEMT 製程並操作於Q 頻段中心頻率為48GHz之功率放大器，其架構為二級功率放大器。我們參考了之前的下線結果，該結果為兩個單級功率放大器，這兩個單級功率放大器電晶體尺寸分別與本章電路驅動級和輸出級相同。透過對這兩個單級功率放大器進行偵錯與重新模擬，並將此結果應用於本章電路設計。量測結果在操作頻率48GHz下增益約為 11.2 dB，OP1dB 為 20.7 dBm，在 P1dB 下的 PAE 結果為 24%。在第四章，我們設計一使用WIN100-nm GaAs pHEMT 製程並操作於D 頻段中心頻率為155GHz 之功率放大器，其架構為單級和四級放大器。，此四級功率放大器各電晶體尺寸與本章節單級相同。透過對此單級功率放大器進行偵錯與重新模擬，並將此結果應用於本章電路設計。量測結果在操作頻率155GHz下增益約為18.6 dB，OP1dB 為 2.2 dBm，Psat 約為 5 dbm。;This thesis focuses on the design and analysis of power ampli ers. The WIN 120-nm GaN on SiC HEMT and WIN 100-nm GaAs pHEMT processes provided by WIN Semiconductors are utilized to implement power ampli ers with various circuit architectures. In Chapter 1, the research motivation and background of this thesis are presented. In Chapter 2, a power ampli er operating in the Q-band with a center frequency of 40 GHz is redesigned and implemented using the WIN 120-nm GaN on SiC HEMT process. The measured small-signal results show good agreement with the simulation results. For large signal measurements, the power ampli er achieves an OP1dB of 21.6 dBm at 40 GHz, and a power-added e ciency PAE of 10.8% at P1dB. In Chapter 3, a power ampli er operating in the Q-band with a center frequency of 48 GHz is designed using the WIN 100-nm GaAs pHEMT process. The circuit adopts a two-stage power ampli er archi tecture. The design is based on previously fabricated single-stage power ampli ers, whose transistor sizes are identical to those of the driver stage and output stage in this chapter. By performing circuit debugging and re-simulation based on the measured results of these single-stage am pli ers, the revised simulation results are applied to the circuit design. Measurement results indicate that the proposed power ampli er achieves a gain of approximately 11.2 dB at 48 GHz, with an OP1dB of 20.7 dBm and a PAE of 24% at P1dB. In Chapter 4, a power ampli er operating in the D-band with a II center frequency of 155 GHz is designed using the WIN 100-nm GaAs pHEMT process. Both single-stage and four-stage ampli er con gura tions are implemented, where the transistor sizes of each stage in the four-stage ampli er are identical to those of the single-stage ampli er. By debugging and re-simulating the single-stage power ampli er, the re ned simulation results are applied to the design of the four-stage am pli er. Measurement results show that the proposed four-stage power ampli er achieves a gain of approximately 18.6 dB at 155 GHz, with an OP1dB of 2.2 dBm。
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