針對數位記憶體內運算 MAC 操作之自動化測試生成：一種故障本質結構適應與多目標成本導向之方法;Automatic Test Generation for MAC Operations in Digital CIM: A Fault-Intrinsic Structure Adaptive and Multi-Objective Cost-Driven Approach

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Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/99447

Title:	針對數位記憶體內運算 MAC 操作之自動化測試生成：一種故障本質結構適應與多目標成本導向之方法;Automatic Test Generation for MAC Operations in Digital CIM: A Fault-Intrinsic Structure Adaptive and Multi-Objective Cost-Driven Approach
Authors:	林威宏;Lin, Wei-Hung
Contributors:	電機工程學系
Keywords:	記憶體內運算;累加操作;自動化測試生成;瑕疵模擬;多目標成本優化;Computing-in-memory;MAC operations;automatic test generation;fault simulation;multi-objective optimization
Date:	2026-01-22
Issue Date:	2026-03-06 19:00:57 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著人工智慧應用的快速發展，傳統馮諾依曼架構因記憶體與處理單元的分離，面臨嚴峻的頻寬瓶頸與高能耗問題。為解決資料搬運瓶頸，數位記憶體內運算（Digital Computing-in-Memory, DCIM）架構應運而生，透過將運算邏輯嵌入記憶體陣列，實現高並行度的乘積累加（MAC）運算。然而，DCIM 架構的整合導致了嚴峻的測試挑戰：MAC 操作的全域廣播機制違反了傳統記憶體測試的位元獨立性假設，且位元乘法邏輯的不對稱性破壞了故障對稱性，使得傳統啟發式測試生成方法與人工分析失效。為解決這些限制，本研究提出一套基於模擬器的結構自適應測試自動生成（ATG）框架。本框架核心在於「十字型狀態」（Cross-Shape State, CSS）故障模型，該模型將複雜的故障機制與全域陣列幾何解耦，將狀態驗證的複雜度相對於記憶體規模 N 降低至 O\left(1\right) 常數級效率。基於此高效模擬模型，本框架整合了詳細的故障致敏與遮蔽回饋機制，以量化評估操作貢獻度，並驅動具備遮蔽懲罰的多目標貪婪搜尋演算法。實驗結果顯示，本方法生成的 March-like 測試序列能在 16N 的線性複雜度內達成 100% 的故障覆蓋率，顯著優於現有文獻中的手動設計方法。;Digital computing-in-memory (CIM) architectures effectively mitigate the von Neumann bandwidth bottleneck by embedding multiply-accumulate (MAC) operations directly within memory arrays. However, the inherent structural dichotomy between the global broadcasting nature of MAC and the bit-independent isolation of SRAM exacerbates test complexity. This conflict leads to an exponential expansion of the fault space and violates the symmetry assumptions of standard automatic test pattern generation (ATPG) flows, rendering manual analysis prohibitive. To overcome this, we propose a simulator-based, structure-adaptive test generation framework. We introduce the cross-shape state (CSS) fault model, which decouples the fault mechanism from array geometry, effectively reducing simulation complexity to O(1) relative to memory scale N. Building upon this efficient simulation foundation, we integrate detailed fault sensitizing and masking feedback to quantify operational contributions. Finally, a multi-objective greedy search with masking penalty is deployed to optimize patterns. Experimental results demonstrate that our approach achieves 100% fault coverage with a compact 16N test sequence, significantly outperforming existing literature.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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