後段製程相容之垂直堆疊式3D 2TnC非揮發性記憶體製程開發與操作;Process Development and Operation of a Back-End-of-Line Compatible Vertically Stacked 3D 2TnC Non-volatile Memory

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Title:	後段製程相容之垂直堆疊式3D 2TnC非揮發性記憶體製程開發與操作;Process Development and Operation of a Back-End-of-Line Compatible Vertically Stacked 3D 2TnC Non-volatile Memory
Authors:	陳佑綺;Chen, You-Chi
Contributors:	電機工程學系
Keywords:	3D;2TnC;垂直結構;3D;2TnC;Vertical structure
Date:	2026-01-23
Issue Date:	2026-03-06 19:01:36 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著半導體製程的持續微縮，傳統非揮發性記憶體在單元面積、儲存密度與後段製程整合性方面逐漸面臨瓶頸。鐵電記憶體因其具備非揮發性、低功耗與高速操作等優勢，被視為下一代記憶體的重要候選技術。然而，平面式鐵電電容在尺寸微縮與多層堆疊的過程中存在挑戰。因此，發展具備後段製程相容性的垂直堆疊式鐵電記憶體架構，成為提升儲存密度與可擴展性的關鍵研究方向。本研究提出並驗證了後段相容性垂直堆疊式 2TnC 非揮發性鐵電記憶體的設計與製程流程。透過多層垂直堆疊結構，成功克服了傳統平面結構中儲存電容面積佔用過大的問題，並在有限的單元面積內實現了穩定的極化行為，顯示出其在高密度非揮發性記憶體應用中的潛力。研究中使用了HZO作為鐵電層，並選用了PEALD製程沉積的IGZO薄膜電晶體作為讀寫元件，經過界面處理與漏電優化，成功實現了單顆電容與多顆電容的記憶體操作。這一成果為未來進一步擴展至多層堆疊結構提供了強有力的實驗依據，並展示了垂直堆疊鐵電記憶體的應用潛力。綜合來看，本研究為高密度非揮發性記憶體的未來發展提供了一個可行的架構，並顯示了進一步優化鐵電材料與電晶體設計的可能性，這將對記憶體的性能提升及高密度儲存技術的應用提供關鍵支持。 ;With the continuous scaling of semiconductor processes, traditional non-volatile memories are gradually facing bottlenecks in terms of unit area, storage density, and BEOL (Back End of Line) process integration. Ferroelectric memories, with their advantages of non-volatility, low power consumption, and high-speed operation, are considered an important candidate technology for next-generation memories. However, planar ferroelectric capacitors face challenges in size scaling and multi-layer stacking. Therefore, the development of a vertically stacked ferroelectric memory architecture compatible with BEOL processes has become a key research direction for improving storage density and scalability. This study proposes and verifies the design and process flow of a BEOL-compatible vertical stacked 2TnC non-volatile ferroelectric memory. Through the multi-layer vertical stacking structure, the issue of large storage capacitor area in traditional planar structures was successfully overcome, achieving stable polarization behavior within a limited unit area, demonstrating its potential in high-density non-volatile memory applications. In the research, HZO was used as the ferroelectric layer, and IGZO thin-film transistors, deposited by the PEALD process, were selected as the read/write elements. After interface treatment and leakage optimization, successful memory operation was achieved with both single and multiple capacitors. This achievement provides a strong experimental foundation for future expansion to multi-layer stacked structures and demonstrates the application potential of vertically stacked ferroelectric memories. In conclusion, this study provides a feasible architecture for the future development of high-density non-volatile memories and shows the potential for further optimization of ferroelectric materials and transistor designs, which will provide key support for performance enhancement and high-density storage technology applications.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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