The layout design of semiconductor bays with spine and perimeter inter-bay guide path loops

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Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/99865

Title:	The layout design of semiconductor bays with spine and perimeter inter-bay guide path loops
Authors:	何應欽;Ho, Ying-Chin;Liao, Ta-Wei
Contributors:	管理學院工業管理研究所
Keywords:	Applied sciences;Assembly lines;bay layout;Bays;Cassettes;Electronics;Exact sciences and technology;Feasibility;Handling operation planning;Heuristic;Inventory control, production control. Distribution;Layouts;Material handling, hoisting. Storage. Packaging;Mathematical analysis;Mathematical models;Mathematical programming;Microelectronic fabrication (materials and surfaces technology);Operational research and scientific management;Operational research. Management science;perimeter guide-path loop;Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices;semiconductor fab;Semiconductors;Spine;spine guide-path loop;Studies
Date:	2012-02-01
Issue Date:	2026-04-21 13:38:50 (UTC+8)
Publisher:	Taylor and Francis Ltd.;Abingdon: Taylor & Francis Group
Abstract:	摘要： In this paper, we study the bay layout problem in a semiconductor fab. One unique characteristic of this bay layout problem is that bays are connected by two inter-bay guide path loops - a spine guide-path loop and a perimeter guide-path loop. To ensure bays can be correctly arranged on the floor and connected by both guide path loops, this dual-loop guide path configuration must be considered throughout the entire layout design procedure. To achieve this goal, we propose a layout design method that considers not only the layout of bays, but also the layout of guide path loops. Furthermore, to ensure the feasibility and quality of the layout results, the proposed layout method solves these two layout problems simultaneously. Since semiconductor fabs often have shortcuts set up on their spine guide path loops, the problem of setting up shortcuts is also studied here. The objective of the proposed layout method is to minimise the total inter-bay flow distance of wafer cassettes. Heuristic methods and mathematical programming models are developed to assist us in achieving this objective. We solved an example problem to illustrate the proposed layout method. The example problem also demonstrates the capability of the proposed layout method in producing feasible and good-quality bay layouts with both spine and perimeter guide path loops. 出版者： Abingdon: Taylor & Francis Group 出版日期： 2012-02-01 出處： International journal of production research, 2012-02, Vol.50 (3), p.719-741 資源來源： EBSCOhost Business Source Premier 版權： Copyright Taylor & Francis Group, LLC 2012 版權： 2015 INIST-CNRS 版權： Copyright Taylor & Francis Group 2012 識別號： ISSN: 0020-7543 識別號： EISSN: 1366-588X 識別號： DOI: 10.1080/00207543.2010.543936 識別號： CODEN: IJPRB8
Appears in Collections:	[Graduate Institute of Industrial Management] journal & Dissertation

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