覆晶封裝中電遷移效應導致之銅溶解現象

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姓名

林永河(Yeong-Her Lin) 查詢紙本館藏

畢業系所

化學工程與材料工程學系

論文名稱

覆晶封裝中電遷移效應導致之銅溶解現象
(Electromigration Induced Cu Dissolution in Flip Chip Packages)

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摘要(中)

本論文報導覆晶封裝之銲點中電遷移所引起之銅墊層快速溶解現象。實驗之試片包含組成為錫鉛共晶之銲點，這些銲點接合了矽晶片與印刷電路板。在矽晶片端之金屬墊層是純銅，而在印刷電路板端之金屬墊層是金/鎳/銅之三層結構。將這些銲點通入不同方向之電流, 電流密度值為 2×104 A/cm2 與 4×104 A/cm2，而環境溫度設定為室溫、70℃與100℃。不論何種電流密度或溫度, 通電之銲點皆因為非對稱之區域性銅溶解現象而失效。此現象發生在陰極電子流入之區域晶片端。這些被溶解之銅會以銅原子之型態遷移至錫鉛銲點中與錫原子反應生成Cu6Sn5之界金屬沉積於陽極電子流出之區域電路板端。造成區域性銅溶解的發生是因為高電流密度所引發的電遷移效應，及巨大的電流密度差所造成之電子流擁擠現象。這些銅溶解之區域會被銲點中之銲料所迴填(銲料移動之方向與電子流相反)。銲點失效之位置皆發生在迴填銲料與殘存銅導線之間，這是因為迴填入導線之錫鉛銲料必須承受更高之電流密度(由於導線之截面積小於銲點之截面積)。然而，電遷移所引起之銅墊層快速溶解並不會發生於印刷電路板端，因為銅上覆蓋一層鎳。而鎳墊層有較好之抗電遷移能力。因此，我們可得知在覆晶封裝應用上，可利用鎳層之保護防止銅溶解現象。

摘要(英)

The phenomenon of Cu dissolution induced by electromigration at flip chip solder joints is reported. A pair of eutectic Sn-Pb solders interconnected between a Si chip and a FR4 substrate is under current stressing with opposite electron current direction. The local current density in the solder ball and in the Cu conducting trace is 2x104 A/cm2 and 4.6x105 A/cm2 respectively. The ambient temperatures are set at 70 oC and 100 oC. The under-bump metallization (UBM) on the chip side is the Cu pad with a conducting trace and on the substrate side is Au/Ni/Cu three-layer structure.
No matter what ambient temperature is, the solder joints failed due to an asymmetrical and localized dissolution of the Cu metallization on the cathode side. The rate of Cu dissolution at the ambient temperature of 100 oC is faster than at 70 oC. The dissolved Cu, including the Cu pad and the Cu conducting trace on the chip side, migrated into solder to form the Cu6Sn5 intermetallics deposited on the substrate side. The Cu atoms drifted to the anode side due to electromigration induced by high current density and current crowding effect caused by huge gradient of current density. The dissolution of Cu coincides with solder back-filled. The site of failure was at the conducting trace that had been back-filled with solder, where a much greater current density was present due to a smaller cross-section.
An in-situ experiment is taken at the current density of 4x104 A/cm2 and room temperature of 30 oC. The phenomenon of Cu dissolution can also be observed on the chip side. Thus, Cu dissolution can be induced at room temperature when the current density is high enough.
The phenomenon of Cu dissolution does not happen on the substrate side, because this Cu is protected by a layer of Ni. Controlling the thickness of Ni UBM can inhibit the electromigration effect in flip chip packages because the Ni has good electromigration resistance.

關鍵字(中)

★ 覆晶封裝
★ 電遷移
★ 銅溶解
★ 銅製程
★ 可靠度

關鍵字(英)

★ Flip chip packages
★ Electromigration
★ Cu dissolution
★ Cu interconnect
★ Reliability

論文目次

CHAPTER 1. Introduction……………...………………1
CHAPTER 2. Literature Review……………….……….5
2.1 Flip chip package……………………………..……………………....5
2.1.1 Introduction of flip chip………………………………………..5
2.1.2 Flip chip process……………………………………………….7
2.1.2.1 Under-bump metallization…….………………………..8
2.1.2.2 Solder bumping………………………………………...8
2.1.2.3 Assembly……………………………………………...13
2.1.2.4 Underfilling…………………………………………...14
2.1.3 Types of flip chip bump structures……………………………14
2.1.4 Benefits of flip chip…………………………………………..16
2.2 Electromigration………………………………………………..…...17
2.2.1 Introduction of electromigration……………………………...17
2.2.2 Driving force of electromigration……………………….…….18
2.2.3 Measurement of electromigration…………………………….21
2.2.4 Joule heating effect……………………………………………24
2.2.5 MTTF of electromigration…………………………………….26
2.3 Electromigration in Sn-Pb solder stripes & lines…………….……..27
2.3.1 Electromigration in solder stripes……………………………..27
2.3.2 Electromigration in solder lines……………………………….31
2.4 Electromigration in flip chip solder joints…………………………..33
2.5 Thermomigration in Sn-Pb solder joints……………………………40
CHAPTER 3. Experiments……………………...…….43
3.1 Samples preparation………………………………………..……….44
3.1.1 Chip side………………………………………………………44
3.1.2 Substrate side………………………………………………….47
3.1.3 Solder joints…………………………………………………...48
3.2 Applying current……………………………………………..……...50
3.2.1 Part A: Applying current on different flip chip packages……..50
3.2.2 Part B: In–situ experiments during current stressing………....52
3.3 Measurement of chip surface temperature………………...………...54
3.4 Metallurgical analysis……………………………………………….56
3.4.1 Metallurgical analysis of part A samples……………………...56
3.4.2 Metallurgical analysis of part B samples……………………..56
CHAPTER 4. Results………………………………….57
Part A: Applying current on different flip chip packages
4.1 Temperature distribution on the chip………………………………..57
4.2 Phenomena of Cu dissolution…………………………………...…..64
4.3 Migration of Pb-rich phase……………………………………...…..83
4.4 Formation of intermetallics……………………………………...….87
Part B: In-situ experiments during current stressing
4.5 In-situ temperature record…………………………………………..89
4.6 In-situ observation of Cu dissolution…………………………...…..90
CHAPTER 5. Discussion………………………….....102
CHAPTER 6. Conclusion…………………………....107
CHAPTER 7. Future Work…………………………..109
References……………………………………………111

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指導教授

高振宏(C. Robert Kao)

審核日期

2003-6-30

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