應用氮化鎵 /砷化鎵積體被動元件與氮化鎵單石 微波積體電路製程於 n79頻段之 多悌 功率放大 器

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姓名

黃子育(Huang, Tzu-Yu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用氮化鎵 /砷化鎵積體被動元件與氮化鎵單石微波積體電路製程於 n79頻段之多悌功率放大器
(Implementations on n79-band GaN Doherty Power Amplifiers with GaAs Integrated Passive Device and Monolithic Microwave Integrated Circuit Processes)

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摘要(中)

本篇論文主要探討多悌功率放大器之架構以及其設計方式，採用製程為穩懋半導體WIN IPD以及 WIN 0.25 μm GaN，操作頻率設計於 5G NR之 n79頻段。其特性為高輸出功率以及高效率，並在功率回退時保持一定之功率增進效率。第一組晶片為使用異質整合設計之功率放大器，操作頻率設計於 C波段，其架構分為輸入網路、核心電路以及輸出網路三個部分，其輸入網路以及輸出網路為被動電路，使用 WINTM IPD之積體被動元件進行整合式設計，核心電路使用 WIN 0.25 μm GaN之電晶體，三個部分使用打線連結組裝。 4.2 GHz量測之增益為 9.38 dB 3 dB頻寬為34%，飽和輸出功率為 36.95 dBm PAE峰值為 PAE於 6 dB功率回退點為EVM使用 256 QAM之 5G NR調變訊號量測於 31.25 dBm會達到 ACPR於高功率輸出為 35.3 dBc。第二顆晶片為 WIN 0.25 μm GaN製程所設計之單石積體電路功率放大器，操作頻段設計於 C波段，設計之最大輸出功率為 10 W，且以兩級之設計改善輸出功率低之問題。 4.0 GHz量測之增益為 12.31 dB 3 dB頻寬為 39%，飽和輸出功率為 35.96 dBm
PAE峰值為 PAE於 6 dB功率回退點為 EVM使用 256 QAM之 5G NR調變訊號量測於 30.16 dBm會達到 ACPR於高功率輸出為 33.7 dBc。第三顆晶片為 WIN 0.25 μm GaN製程所設計之單石積體電路功率放大器，操作頻段設計於 C波段，以改善第二顆晶片之低效率以及低增益為主要目的，設計之最大輸出功率為 10 W。 4.8 GHz量測之增益為 14.83 dB 3 dB頻寬為 24%，飽和輸出功率為42.28 dBm PAE峰值為 42.02 PAE於 6 dB功率回退點為 39.30%。

摘要(英)

The thesis implemented three power amplifiers and focused on Doherty power amplifier design methodology. The adopted technologies are WIN IPD and 0.25 μm GaN/SiC processes. The operation frequency was chosen at n79 band of 5G NR. The performance calls for keeping its high efficiency at required output power back off. The first chip is a C-band power amplifier which is divided into three parts, i.e., input matching network, transistors and output matching network. The input/output match networks were realized by WIN IPD process and the transistor was used WINTM 0.25 μm GaN process separately. Then, they were assembled in an FR 4 PCB via chip and wire technique. The measured power gain was 9.38 dB with a 3 dB bandwidth of 34%. The saturation power was measured as 36.95 dBm with a peak PAE of 36.91%. A 28.89% PAE was obtained at 6 dB output back off. The modulated signal measurements were performed as below, 3.5% EVM was measured at output power of 31.25 dBm under 5G NR 256 QAM modulation scheme. Meanwhile, the ACPR measurement result was 35.3 dBc. The second C-band MMIC power amplifier was realized in WIN 0.25 μm GaN/SiC process. The measured power gain was 12.31 dB with a 3 dB bandwidth of 39%. The saturation power was measured as 35.96 dBm with a peak PAE of23.57%. A 21.01% PAE was obtained at 6 dB output back off. The modulated signal measurements were performed as below, 3.5% EVM was measured at output power of 30.16 dBm under 5G NR 256 QAM modulation scheme. Meanwhile, the ACPR measurement result was 33.7 dBc. The third MMIC, which designed for n79 band, was realized in WIN 0.25 μm GaN/SiC and the type. The target was improve the low gain of second chip. The simulated power gain was 14.83 dB with a 3 dB bandwidth of 24%; the simulated saturation power was 42.28 dBm, with a PAE peak of 42.02% and a 6 dB output back off of 39.30%.

關鍵字(中)

★ 功率放大器
★ 發射機
★ 第五代行動通訊
★ 氮化鎵
★ 砷化鎵
★ 積體被動元件

關鍵字(英)

★ Power Amplifiers
★ 5G-NR
★ n79
★ GaN
★ Doherty PA
★ IPD

論文目次

摘要 VIII
Abstract IX
誌謝 XI
目錄 XII
圖目錄 XIII
表目錄 XVI
第一章緒論 1
1-1 研究動機 1
1-2 實驗室研究計畫 2
1-3 章節說明 3
第二章應用氮化鎵 /砷化鎵積體被動元件之功率放大器設計 4
2-1 多悌功率放大器簡介 4
2-2 阻抗調變原理 6
2-3 氮化鎵 /砷化鎵積體被動元件功率放大器架構 9
2-4 打線電感模擬 11
2-5 寬邊耦合器設計與模擬 13
2-6 整體電路模擬結果 16
2-7 電路模擬以及量測結果比對 20
第三章寬頻多悌功率放大器設計 33
3-1 寬頻多悌功率放大器架構 33
3-2 Lange耦合器設計簡介 35
3-3 整體電路模擬結果 38
3-4 電路模擬以及量測結果比對 44
第四章高效率多悌功率放大器設計 58
4-1 多悌功率放大器技術總結 58
4-2 高效率多悌功率放大器架構詳述 59
4-3 Lange耦合器設計詳述 61
4-4 輸出負載設計 63
4-5 電路佈局以及模擬結果 65
第五章結論 69
5-1 結論 69
參考文獻 71

參考文獻

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2021-8-26

推文