使用傳輸線基準全通網路之全差動式 Ka 頻段 五位元 CMOS 相位偏移器

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姓名

黃祖德(Tsu-De Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用傳輸線基準全通網路之全差動式 Ka 頻段五位元 CMOS 相位偏移器
(Fully-Differential Ka-Band 5-Bit CMOS Phase Shifters Using Transmission-Line-Based Quasi-All-Pass Networks)

相關論文

★ 分佈式類比相位偏移器之設計與製作	★ 以可變電容與開關為基礎之可調式匹配網路應用於功率放大器效率之提升
★ 全通網路相位偏移器之設計與製作	★ 使用可調式負載及面積縮放技巧提升功率放大器之效率
★ 應用於無線個人區域網路系統之低雜訊放大器設計與實現	★ 應用於極座標發射機之高效率波包放大器與功率放大器
★ 數位家庭無線資料傳輸系統之壓控振盪器設計與實現	★ 鐵電可變電容之設計與製作
★ 用於功率放大器效率提升之鐵電基可調式匹配網路	★ 基於全通網路之類比式及數位式相位偏移器
★ 使用鐵電可變電容及PIN二極體之頻率可調天線	★ 具鐵電可變電容之積體被動元件製程及其應用於微波相位偏移器之製作
★ 使用磁耦合全通網路之寬頻四位元 CMOS相位偏移器	★ 具矽基板貫孔之鐵電可變電容的製作與量測
★ 矽基板貫孔的製作和量測	★ 使用鐵電可變電容之頻率可調微帶貼片天線

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至系統瀏覽論文 (2025-7-31以後開放)

摘要(中)

Ka 頻段（26.5–40 GHz）是目前應用於第五代行動通訊之頻段，
此頻段的頻寬較大，有更高的傳輸速率、更短的延遲。無論是第五代
行動通訊還是雷達系統，在此頻帶中，我們都需要相位陣列去支援更
多的應用。相位偏移器則是相位陣列中最為關鍵的電路之一，藉由提
供相位陣列中各天線可調變的相位差，即可改變相位陣列發射與接收
的方向。相移器的主要的設計方向有較高的相位解析度、頻寬、較小
的相位誤差、振幅誤差、較低的植入損耗、直流功耗，以及整體晶片
面積的考量。在本論文中，我們使用 TSMC 90-nm CMOS 製程來實
現 Ka 頻段的全差動式五位元相位偏移器。

在第二章中，我們使用 TSMC 90-nm CMOS 製程設計 Ka 頻段五位元被動式相位偏移器。電路的操作頻率為 35 GHz，其中 11.25◦、22.5◦、45◦及 90◦相位偏移器都是使用傳輸線基準全通網路架構，180◦相位偏移器則是使用 SPDT (single pole double throw) 開關實現。我們使用Keysight ADS 進行電路模擬，並將傳輸線的部分進行電磁模擬，模擬結果顯示，均方根相位誤差低於 3◦內，其對應到的頻率範圍為 31.8–41.5 GHz，頻寬可達 26.46 %，輸入返回損耗在頻寬內皆大於 19.3 dB，輸出返回損耗在頻寬內皆大於 14.5 dB。植入損耗在頻寬內皆小於 18.4 dB。平均植入損耗在頻寬內皆小於 17.1 dB。振幅誤差皆在 ±1.44 dB 以內，均方根振幅誤差最差為 0.91 dB 。IP1dB 於35 GHz 時約為 24–26 dBm，晶片面積為 1× 1.25 mm2。接著我們使用Keysight N5227B 4-port 網路分析儀量測小訊號 S 參數。量測結果顯示，所有狀態的相位偏移量皆有變大且往高頻頻偏的趨勢，均方根相位誤差也上升至 11.5◦，因此我們重新定義頻寬為 27.7–45.2 GHz。在頻段內，返回損耗皆大於 10 dB，植入損耗在頻寬內均小於 17.5 dB，振幅誤差皆在 ±1.3 dB 以內。我們為了改善量測結果去做重新模擬，我們猜測 MIM 電容 model 上的寄生電感比實際上的少，因此我們在MIM 電容旁邊串聯電感，以確保 model 與實際上的寄生電感不會相差太多，各級串聯電感後，相位偏移量能夠變大且跟量測結果相近，均方根相位誤差與相移量均有符合量測結果的趨勢。

在第三章中，我們使用 TSMC 90-nm CMOS 製程設計 Ka 頻段五位元被動式相位偏移器。電路的操作頻率為 35 GHz，其中的 11.25◦、22.5◦、45◦及 90◦相位偏移器都是使用傳輸線基準全通網路的架構，其中為了使 90◦相移級的頻寬不限制住整體的頻寬，我們串接兩個中心頻錯開的傳輸線基準全通網路來提升頻寬。180◦相位偏移器則是使用 SPDT 開關實現。我們使用 Keysight ADS 進行電路模擬，並將傳輸線的部分進行電磁模擬，模擬結果顯示，均方根相位誤差低於 3◦內，其對應到的頻率範圍為 29.1–43.3 GHz，頻寬可達 39.22 %，輸入返回損在頻寬內皆大於 16.8 dB，輸出返回損耗在頻寬內皆大於 12.8 dB。植入損耗在頻寬內皆小於 19.6 dB。平均植入損耗在頻寬內皆小於 19 dB。振幅誤差皆在 ±0.94 dB 以內，均方根振幅誤差最差為 0.55 dB 。IP1dB 於 35 GHz 時約為 26.4–28.6 dBm，晶片面積為 1.36× 1.25mm2。
接著我們使用 Keysight N5227B 4-port 網路分析儀量測小訊號 S 參數。量測結果顯示，所有狀態的相位偏移量皆有變大且往高頻頻偏的趨勢，均方根相位誤差也上升至 11.7◦，因此我們重新定義頻寬為 23.4–48 GHz。在頻段內，返回損耗皆大於 7.7 dB，植入損耗在頻寬內均小於 19.1 dB，振幅誤差皆在 ±0.75 dB 以內。接著我們一樣推論導致相位偏移量頻偏且變大的原因可能是因為 TSMC 90-nm CMOS 製程原本提供的 MIM 電容 model 之寄生電感估的比實際上來的小，因此我們在 MIM 電容旁邊串聯理想電感，將 MIM 電容的寄生電感加回來，使相位偏移量與量測結果貼近，各級補償的電感值和第二章所補償的電感值相同。

在本論文中，我們成功實現了 Ka 頻段的五位元 CMOS 相位偏移器。雖然量測結果與模擬結果相差不小，但經過重新模擬，我們可以知道此製程在 Ka 頻段可能會有哪些影響，考慮完這些影響後，能夠使結果更加接近我們期望的效能。

摘要(英)

Ka band (26.5–40 GHz) is currently used in fifth-generation mobile communications. This frequency band has a large bandwidth, higher transmission rate, and lower latency. Whether it is the fifth-generation mobile communications or radar systems, we need phased arrays to sup- port more applications in this frequency band. The phase shifter is one of the most critical circuits in the phase array. By providing an ad- justable phase difference of each antenna in the phased array, we can control transmitting and receiving direction in phased array . The main considerations of the phase shifter are higher phase resolution, band- width, smaller phase error, amplitude error, lower insertion loss, DC power consumption, and chip area . In this thesis, we use TSMC 90-nm CMOS process to achieve fully-differential Ka-band 5-bit CMOS phase shifters using transmission-line-based quasi-all-pass networks.
In Chapter 2, we use the TSMC 90-nm CMOS process to design a Ka-band 5-bit passive phase shifter. The operating frequency of the circuit is 35 GHz. The 11.25◦, 22.5◦, 45◦ and 90◦ phase shifter use transmission line-based quasi all-pass network architecture, and the 180
◦ phase shifter uses SPDT switch architecture. We use Keysight ADS to
simulate circuit and analyze transmission line by electromagnetic sim- ulation. The simulation results show that the RMS phase error is less than 3◦, the corresponding frequency band is 31.8–41.5 GHz, the band- width is 26.46 %, and the input return loss is greater than 19.3 dB, the output return loss is greater than 14.5 dB over all the bandwidth.

Insertion loss is less than 18.4 dB across the bandwidth. The average insertion loss is less than 17.1 dB across the bandwidth. The amplitude errors is smaller than ±1.44 dB, and the worst RMS amplitude error is
0.91 dB. IP1dB is approximately 24–26 dBm at 35 GHz and the chip area is 1× 1.25 mm2. Then we use Keysight N5227B 4-port network analyzer to measure the S parameters. The measurement results show that the phase shift of all states tends to increase and shift to high frequency, and the root mean square phase error also rises to 11.5◦. Therefore, we
redefine the bandwidth as the 27.7–45.2 GHz. In this band, the return loss is greater than 10 dB, the insertion loss is greater than 17.5 dB, and the amplitude error is within ±1.3 dB. In order to improve the measure- ment results to resimulate, We guess that the parasitic inductance on the MIM capacitor model is less than the actual one. Therefore, we se- ries inductor next to the MIM capacitor to make sure that the parasitic inductance of the model is not too different from the actual parasitic inductance. But we can only make the simulation results close to the measurement results by series inductor.
In Chapter 3, we use the TSMC 90-nm CMOS process to design a Ka-band 5-bit passive phase shifter. The operating frequency of the circuit is 35 GHz. The 11.25◦, 22.5◦, 45◦ and 90◦ phase shifter use trans- mission line-based quasi all-pass network architecture, and the 90 ◦ phase shifter uses two stages of transmission line-based quasi all-pass network with different center frequencies. The network is connected in series, and the center frequencies are 22 GHz (LB) and 52 GHz (HB). The 180 ◦ phase shifter uses SPDT switch architecture. We use Keysight

ADS to simulate circuit and analyze transmission line by electromag- netic simulation. The simulation results show that the RMS phase error is less than 3◦, the corresponding frequency band is 29.1–43.3 GHz, the bandwidth is 39.22 %, and the input return loss is greater than 16.8 dB, the output return loss is greater than 12.8 dB over all the bandwidth. Insertion loss is less than 19.6 dB across the bandwidth. The average
insertion loss is less than 19 dB across the bandwidth. The amplitude errors is smaller than ±0.94 dB, and the worst RMS amplitude error is 0.55 dB. IP1dB is approximately 26.4–28.6 dBm at 35 GHz and the chip area is 1.36× 1.25 mm2. Then we use Keysight N5227B 4-port network analyzer to measure the S parameters. The measurement re-
sults show that the phase shift of all states tends to increase and shift to high frequency, and the root mean square phase error also rises to 11.7◦. Therefore, we redefine the bandwidth as the 23.4–48 GHz. In this band, the return loss is greater than 7.7 dB, the insertion loss is greater than
19.1 dB, and the amplitude error is within ±0.75 dB. We guess that the parasitic inductance on the MIM capacitor model is less than the actual one. Therefore, we series inductor next to the MIM capacitor to make sure that the parasitic inductance of the model is not too different from the actual parasitic inductance. Besides, we series inductor and capacitor next to the MIM capacitor to make sure that simulation is close to measurement. Finally, we can only make the simulation results close to the measurement results by series inductor.

In this paper, we have successfully implemented Fully-Differential Ka-band 5-Bit CMOS Phase Shifters. Although the measurement re- sults are quite different from the simulation results, after resimulating, we can know the effects of this process in the Ka band. After considering these effects, the results can be closer to our expected performance.

關鍵字(中)

★ 相移器

關鍵字(英)

★ Phase Shifters

論文目次

摘要. . . . . . .V
Abstract. . . . . . .VIII
目錄. . . . . . .XII
圖目錄. . . . . . .XIV
表目錄. . . . . . .XIX
第一章緒論 . . . . . . .1
1.1 研究動機 . . . . . . .1
1.2 文獻回顧 . . . . . . .2
1.2.1 相位偏移器文獻回顧. . . . . . .2
1.2.2 Ka 頻段相位偏移器文獻回顧. . . . . . .3
1.3 論文架構 . . . . . . .4
第二章傳輸線基準全通網路之全差動式 Ka 頻段五位元
CMOS 相位偏移器. .. . . . . . . . . . . 5
2.1 簡介. . . . . . . 5
2.2 基於傳輸線的準全通網路之電路分析. . . . . . . 6
2.3 電路設計 . . . . . . . 10
2.3.1 11.25◦、22.5◦、45◦及 90◦相位偏移量. . . . . . . 12
2.3.2 180◦相位偏移器. . . . . . . 19
2.4 模擬結果 . . . . . . . 22
2.5 量測結果 . . . . . . . 31
2.6 重新模擬 . . . . . . . 37
2.7 結論. . . . . . . 43
第三章使用傳輸線基準全通網路之全差動五位元 CMOS 寬
頻相位偏移器. . . . . . . 45
3.1 簡介. . . . . . . 45
3.2 電路設計. . . . . . . 46
3.2.1 11.25◦、22.5◦、45◦及 90◦相位偏移量. . . . . . . 48
3.2.2 180◦相位偏移器. . . . . . . 54
3.3 模擬結果. . . . . . . 56
3.4 量測結果. . . . . . . 64
3.5 重新模擬. . . . . . . 70
3.6 結論. . . . . . . 75
第四章結論. . . . . . . 77

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指導教授

傅家相(Jia-Shiang Fu)

審核日期

2022-9-7

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