具資料序列偵測器之6 Gbps全速率時脈與資料回復電路

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姓名

葉又慈(Yu-Tzu Yeh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具資料序列偵測器之6 Gbps全速率時脈與資料回復電路
(A 6 Gbps Full-Rate Clock and Data Recovery Circuit with Data Pattern Detector)

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至系統瀏覽論文 (2028-7-31以後開放)

摘要(中)

近年來隨著半導體產業的蓬勃發展，產品應用上所需之資料傳輸頻寬也不斷提高，傳輸介面中，並列傳輸介面因為成本較高的問題，已逐漸被高速串列傳輸介面所取代，隨著串列傳輸系統的傳輸速率提升，抖動對資料的影響佔比越加顯著，在電路的設計上也更加有難度，因此在時脈與資料回復電路的中，優化抖動容忍度並且降低追鎖抖動將成為設計首要目標。
本論文實現一具有資料序列偵測器之6 Gbps全速率時脈與資料回復電路，提出資料序列偵測器的做法，針對相位追蹤補償相位偵測器在遇到長時間不轉態的輸入資料時，會產生與輸入資料不轉態資料筆數相同之長輸出脈波訊號，使得系統有較大的追鎖抖動的問題做改善，資料序列偵測器在偵測到長0或長1的資料序列時，會產生控制訊號，將電荷幫浦的充放電路徑的開關關閉，藉此降低還原時脈的抖動量。透過結合資料序列偵測器與相位追蹤補償相位偵測器的做法，成功達到降低追鎖抖動與良好的抖動容忍度表現。本論文使用TSMC 90 nm 1P9M (TN90GUTM) CMOS 製程實現，操作電壓為1.0 V，輸入資料速率為6 Gbps，輸出還原時脈訊號為6 GHz，當輸入PRBS31的資料時，開啟資料序列偵測器下的還原時脈之抖動峰對峰值為9.24 ps，抖動方均根植為3.14 ps，與未開啟資料序列偵測器的還原時脈抖動峰對峰值相比於後模擬中有27.24%的改善量，功率消耗為33.00 mW，核心電路面積為0.087 mm2，晶片面積為1.59 mm2。

摘要(英)

In recent years, with the rapid development of the semiconductor industry, the requirement of data transmission bandwidth for product applications has also increased. Among the transmission interfaces, the parallel transmission interface has gradually been replaced by the high-speed serial transmission interface due to cost-related issues. With the increasing transmission rate of the serial transmission interface, the impact of jitter on the data becomes more significant, and circuit design becomes more challenging. Therefore, optimizing jitter tolerance and reducing jitter in the clock and data recovery circuit will be the primary design goal.
This thesis implements a 6 Gbps full-rate clock and data recovery circuit with a data pattern detector. The proposed CDR presents a data pattern detector(DPD) which improved the drawback of phase tracking compensation phase detector(PTCPD). When input data has a long consecutive identical digits(CID), PTCPD will generates a long pulse-width output signal with the same bits of consecutive non-transition data. This case will increase the recovered clock jitter. When DPD detects long sequences of 0 or 1 data, it generates control signal which disables the charging and discharging path of the charge pump. This reduces the jitter of recovered clock. By using the DPD and the PTCPD, the circuit achieves improved jitter of recovered clock and robust jitter tolerance performance. The chip is fabricated by TSMC 90 nm 1P9M (TN90GUTM) CMOS process. With a supply voltage of 1.0 V, input data rate of 6 Gbps, and produces an output recovered clock signal at 6 GHz. When the PRBS31 data is inputted, the post-layout simulation results of the recovered clock peak-to-peak jitter is 9.24 ps and a root mean square jitter is 3.14 ps. The proposed CDR with DPD represents a 27.24% improvement in recovered clock peak-to-peak jitter compared to the CDR without DPD. The power consumption is 33.00 mW. The core area is 0.087 mm2, and the chip area is 1.59 mm2.

關鍵字(中)

★ 時脈與資料回復電路

關鍵字(英)

★ CDR

論文目次

摘要 i
Abstract ii
目錄 iv
圖目錄 viii
表目錄 xiv
第一章緒論 1
1.1研究動機 1
1.2 論文架構 4
第二章高速串列傳輸系統背景介紹 5
2.1 隨機二元資料 5
2.1.1 隨機二元資料型態 5
2.2.2 隨機二元資料特性 6
2.1.3 資料編碼方式 7
2.2 抖動介紹 8
2.2.1 隨機性抖動(Random Jitter, RJ) 9
2.2.2定量性抖動 10
2.2.2.1資料相關抖動 10
2.2.2.2 責任週期失真 11
2.2.2.3週期性抖動 12
2.2.3抖動量測方式 13
2.2.3.1時間間隔誤差抖動 13
2.3.3.2 週期抖動 14
2.3.3.3相鄰週期抖動 14
2.3眼圖分析 15
2.4誤碼率 16
第三章時脈與資料回復電路背景介紹 20
3.1 時脈與資料回復電路簡介 20
3.1.1 相位偵測器分類 21
3.1.1.1 相位偵測器取樣速率[8] 21
3.1.1.2相位偵測器型態 22
3.1.2抖動轉移函數(Jitter Transfer, JTF) 23
3.1.3 抖動容忍度(Jitter Tolerance, JTOL) 24
3.1.3.1轉態密度對抖動容忍度之影響[7] 25
3.1.3.2 迴路延遲對抖動容忍度之影響[7] 27
3.1.4抖動產生(Jitter Generation) 28
3.2時脈與資料回復電路相關設計 28
3.2.1 多增益路徑之超取樣式時脈與資料回復電路[18]-[20] 28
3.2.2自適應迴路增益之時脈與資料回復電路[21]-[23] 30
3.2.3具相位追蹤補償技術之時脈與資料回復電路[7] 31
3.3比較與討論 32
第四章具資料序列偵測器之全速率時脈與資料回復電路設計與實現 33
4.1電路架構 33
4.2系統分析 36
4.2.1 頻率資訊迴路系統分析 36
4.2.2相位資訊迴路系統分析 39
4.3 資料序列偵測器之設計 44
4.4所提出之時脈與資料回復電路之行為模擬 46
4.5所提出之時脈與資料回復電路子電路介紹 48
4.5.1相位追蹤補償相位偵測器(Phase Tracking Compensation Phase Detector, PTCPD) 48
4.5.2 資料序列偵測器(Data Pattern Detector, DPD) 51
4.5.3 相位頻率偵測器(Phase Frequency Detector, PFD) 52
4.5.4 電荷幫浦(Charge Pump) 54
4.5.5迴路濾波器(Loop Filter, LF) 56
4.5.6壓控振盪器(Voltage Controlled Oscillator, VCO) 57
4.5.7除頻器(Divider, DIV) 59
4.6 模擬結果 60
4.6.1 佈局前模擬結果 60
4.6.2 佈局後模擬結果 65
第五章晶片佈局與量測 71
5.1 電路佈局 71
5.1.1晶片封裝 72
5.1.2電源佈局與規劃 74
5.2量測考量 75
5.2.1量測環境 75
5.2.2高頻輸入緩衝器 76
5.2.3高頻輸出緩衝器 77
5.2.4低頻輸出緩衝器 78
5.3規格比較表 79
第六章結論 81
6.1結論 81
6.2未來研究方向 82
參考文獻 83
附錄一 87
I. 判斷還原資料正確性之方法 87
i. 偽亂數二進位數列產生器與偽亂數二進位數列檢查器(PRBS Generator & PRBS Checker) 87

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2023-7-24

推文