應用於第五代無線通訊之結合Cold-FET預失真線性化電路互補式金氧半導體堆疊式功率放大器暨25%責任週期I/Q發射機研製

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廖弘智(Hong-Zhi Liao) 查詢紙本館藏

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電機工程學系

論文名稱

應用於第五代無線通訊之結合Cold-FET預失真線性化電路互補式金氧半導體堆疊式功率放大器暨25%責任週期I/Q發射機研製
(Implementations on CMOS Stacked Power Amplifier with Cold-FET Predistortion Linearizer and 25% Duty Cycle I/Q Transmitter for Fifth-Generation Wireless Communication Applications)

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至系統瀏覽論文 (2029-5-1以後開放)

摘要(中)

本論文使用台灣積體電路製造股份有限公司018-µm CMOS 製程設計應用於 n77-n79 頻段之結合 Cold-FET 線化電路之互補式金氧半導體堆疊式功率放大器以及應用於 n79 頻段之 25%責任週期之 I/Q 發射機之設計。
第一顆提出應用於 n77-n79 頻段之結合 Cold-FET 線性化電路之互補式金氧半導體功率放大器，使用堆疊式架構改善 CMOS 製程電晶體本身低崩潰電壓及高膝部電壓之限制，改善電路整體輸出功率，電路匹配採用對稱式磁耦合共振腔變壓器進行設計，達到寬頻之效果，並且在驅動級放大器前置入 Cold-FET 線性化器電路，透過線性化之啟動，使得電路達到增益擴展的效果，達成拉近輸出 1-dB 增益壓縮點功率與輸出飽和功率之間的距離。其操作頻寬為 2.9 - 5 GHz，最大傳輸增益為 21.8 dB，最大輸出功率為27.24 dBm，1-dB 增益壓縮點輸出功率在開啟線性化器後為 26.72 dBm，最高附加效率為 25.57%，晶片面積為 3.69 mm2(2.7 mm × 1.37 mm)
第二顆晶片提出應用於 n79 頻段之四分之一責任週期之 I/Q 發射機電路，本地震盪端口使用電流模態邏輯除頻器後接上方波緩衝器產生四相位訊號，混頻後訊號透過 I/Q路徑直接結合方式求得上邊帶頻率。量測時固定本地震盪驅動訊號為 6 dBm時，操作頻帶為 3 - 4.3 GHz，量測到最大轉換增益為 8.6 dB，輸出 1-dB增益壓縮點功率為 4.61 dBm，輸出三階截斷點為 8.92 dBm，發射機之最佳載波抑制量為 45.3 dBc，最佳邊帶抑制量為44.6 dBc，晶片面積為 1.59 mm2(1.6 mm × 0.98 mm)。

摘要(英)

This thesis introduces the design of a complementary metal-oxide-semiconductor (CMOS) stacked power amplifier tailored for the n77-n79 frequency bands, integrating a unified ColdFET linearization circuit. The implementation utilizes Taiwan Semiconductor Manufacturing Company′s (tsmc™) 018-µm CMOS process. Furthermore, it presents a 25% duty cycle I/Q
transmitter intended for the n79 frequency band.
The first chip demonstrates a CMOS power amplifier for the n77-n79 frequency bands, which employed a stacked architecture to overcome inherent limitations in the CMOS process, such as the low breakdown voltage and high knee voltage of the transistors. This configuration significantly enhances the overall circuit output power.
Notably, a symmetrically coupledresonator transformer is incorporated for circuit matching, enabling broadband performance. Integration of a Cold-FET linearization circuit before the driver amplifier facilitates gain expansion, reducing the gap between the output 1-dB gain compression point power and the output saturation power. Operating within the bandwidth of 2.9 - 5 GHz, the chip achieves a
maximum gain of 21.8 dB, a maximum output power of 27.24 dBm, a 1-dB gain compression point output power of 26.72 dBm and a peak power added efficiency of 25.57% as post linearizer activation. The chip′s physical footprint measures 3.69 mm² (2.7 mm × 1.37 mm).
The second chip focuses on a 25% duty cycle I/Q transmitter circuit tailored for the n79 frequency band. The local oscillator port employs a current-mode logic divider followed by a iii square wave buffer to generate quadrature-phase signals. The mixed signal, achieved through direct combination in the I/Q path, produces the upper sideband frequency. Operating within the range of 3 - 4.3 GHz with an optimal local oscillator drive signal of 6 dBm, this chip achieves a maximum conversion gain of 8.6 dB, a 1-dB gain compression point output power of 4.61 dBm, and a third-order intercept point of 8.92 dBm. Impressively, the transmitter demonstrates excellent carrier suppression of 45.3 dBc and sideband suppression of 44.6 dBc.The chip occupies an area of 1.59 mm² (1.6 mm × 0.98 mm).

關鍵字(中)

★ 功率放大器
★ 冷場效電晶體
★ IQ發射機
★ 四分之一責任週期

關鍵字(英)

★ Power amplifier
★ Cold-FET transistor
★ IQ transmitter
★ 25% duty cycle

論文目次

摘要 .............................................................................................................................................i
Abstract....................................................................................................................................... ii
致謝 ........................................................................................................................................... iv
目錄 ........................................................................................................................................... vi
圖目錄 ......................................................................................................................................viii
表目錄 ....................................................................................................................................... xi
第一章緒論 ........................................................................................................................1
1-1 研究動機 ................................................................................................................1
1-2 研究成果 ................................................................................................................2
1-3 章節簡介 ................................................................................................................2
第二章結合 Cold-FET 線性化器之互補式金氧半導體堆疊式功率放大器 ..................3
2-1 研究現況 ................................................................................................................3
2-2 堆疊式功率放大器架構簡介 ................................................................................6
2-3 磁耦合共振腔簡介 ................................................................................................8
2-4 Cold-FET 線性化結構簡介 ................................................................................. 11
2-5 應用於 n77~n79 頻段之結合 Cold-FET 線性化器之堆疊式功率放大器.......14
2-5-1 電路圖 ......................................................................................................14
2-5-2 電晶體偏壓選擇 ......................................................................................15
2-5-3 輸出匹配網路設計 ..................................................................................17
2-5-4 級間與輸入匹配網路設計 ......................................................................23
2-5-5 Cold-FET 預失真電路設計 ....................................................................30
2-5-6 電路模擬與量測結果 ..............................................................................31
2-5-7 結果比較與討論 ......................................................................................48
第三章應用於 n79 頻段之 25%責任週期之 I/Q 發射機...............................................52
3-1 研究現況 ..............................................................................................................52
3-2 電路架構與設計原理 ..........................................................................................53
3-2-1 IQ 訊號產生器-除頻器電路設計...........................................................58
3-2-2 發射機混頻器選擇-電流模態被動混頻器.............................................61
3-2-3 中頻反向式緩衝放大器 ..........................................................................69
3-2-4 驅動功率放大器 ......................................................................................72
3-2-5 量測與模擬比較 ......................................................................................77
3-2-6 結果比較與討論 ......................................................................................87
第四章結論 ......................................................................................................................91
4-1 總結 ......................................................................................................................91
4-2 未來研究方向 ......................................................................................................92
參考文獻 ..................................................................................................................................93

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2024-6-21

推文