具自適應且多階資料獨立相位追蹤補償技術之 5 Gbps 半速率時脈與資料回復電路

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姓名

蘇姿羽(Tzu-Yu Su) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具自適應且多階資料獨立相位追蹤補償技術之 5 Gbps 半速率時脈與資料回復電路
(A 5 Gbps Half-Rate Clock and Data Recovery with Adaptive Multi-level Data Independent Phase Tracking Compensation Technique)

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至系統瀏覽論文 (2028-10-31以後開放)

摘要(中)

近年隨著先進製程的演進以及產品應用上的需求，資料在傳輸速率方面也跟著大幅提升，現今傳輸介面上，已由高速串列傳輸主導，例如：PCI Express、Ethernet、USB及HDMI等。然而當資料速率不斷提升，即位元週期不斷縮小下，抖動對於資料的佔比將更加嚴重，並且電路的時間餘裕也將越來越限縮，導致抖動容忍度惡化以及誤碼率提升，因此如何降低追鎖抖動以及改善抖動容忍度在電路設計上至關重要。

本論文遵循USB 3.2 Gen1的通訊規範，實現一個具自適應且多階資料獨立相位追蹤補償技術之5 Gbps半速率時脈與資料回復電路。

摘要(英)

In recent years, with the advanced process technology and the increasing demand for product applications, data transmission rates have significantly increase. Nowadays, high-speed serial link has become dominant in transmission interfaces, such as PCI Express, Ethernet, USB, and HDMI. However, as data rates continue to increase and unit interval continue to shrink, jitter becomes the significant issue, and the timing margin in circuits become increasingly constrained, leading to worse jitter tolerance and higher bit error rate. Therefore, reducing hunting jitter and improving jitter tolerance are crucial in circuit design.

This thesis adheres to the USB 3.2 Gen1 communication specification and implements a 5 Gbps half-rate clock and data recovery circuit with adaptive and multi-level data independent phase tracking compensation technology.

關鍵字(中)

★ 時脈與資料回復電路

關鍵字(英)

★ CDR

論文目次

摘要 i
Abstract iii
誌謝 v
目錄 vi
圖目錄 x
表目錄 xiii
第 1 章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第 2 章高速串列傳輸系統基本概述 5
2.1 隨機二位元資料 5
2.1.1 隨機二位元資料之面臨問題 5
2.2 抖動介紹 7
2.2.1 隨機性抖動(Random Jitter, RJ) 8
2.2.2 定量性抖動 9
2.2.2.1 資料相關抖動 9
2.2.2.2 責任週期失真 11
2.2.2.3 週期性抖動 12
2.2.3 抖動量測方式 13
2.2.3.1 時間間隔誤差 14
2.2.3.2 週期抖動 15
2.2.3.3 相鄰週期抖動 16
2.2.3.4 抖動量測方式之總結 17
2.3 眼圖分析 18
2.4 誤碼率[16] 19
第 3 章時脈與資料回復電路背景介紹 22
3.1 時脈與資料回復電路簡介 22
3.1.1 相位偵測器操作型態 23
3.1.2 相位偵測器取樣速率 24
3.1.3 抖動轉移函數(Jitter Transfer, JTF) 25
3.1.4 抖動容忍度 26
3.1.4.1 迴路延遲對抖動容忍度之影響[6] 27
3.1.5 抖動產生(Jitter Generation)[22] 28
3.2 傳統時脈與資料回復電路相關設計 28
3.2.1 鎖相迴路式時脈與資料回復電路 28
3.2.2 混合鎖相迴路及延遲鎖定迴路式時脈與資料回復電路 30
3.2.3 超取樣式時脈與資料回復電路 31
3.2.4 相位內插式時脈與資料回復電路 32
3.2.5 突發模式時脈與資料回復電路 33
3.2.6 頻率資訊迴路 34
3.3 提高抖動容忍度之設計背景 36
3.3.1 多增益路徑之超取樣式時脈與資料回復電路 36
3.3.2 自適應迴路增益之時脈與資料回復電路 38
3.4 分析與比較 39
3.5 論文貢獻與特色 40
第 4 章具自適應且多階資料獨立相位追蹤補償技術之半速率時脈與資料回復電路設計與實現 42
4.1 電路架構 42
4.2 系統分析 45
4.2.1 頻率資訊迴路系統分析 45
4.2.2 相位資訊迴路系統分析 49
4.3 多階相位追蹤補償相位偵測器操作說明 55
4.3.1 傳統二進位相位偵測器電路分析 55
4.3.2 多階相位追蹤補償相位偵測器分析 56
4.4 子電路介紹 58
4.4.1 傳統半速率二進位相位偵測器 58
4.4.2 多階相位追蹤補償相位偵測器 60
4.4.3 相位偵測器選擇電路 63
4.4.4 電荷幫浦 64
4.4.5 電容放大技術之迴路濾波器 66
4.4.6 壓控振盪器 67
4.4.7 擺幅轉換電路 69
4.4.8 除頻器 69
4.4.9 相位頻率偵測器 70
4.5 模擬結果 72
4.5.1 佈局前模擬 72
4.5.2 佈局後模擬 76
第 5 章晶片佈局與量測 80
5.1 電路佈局 80
5.1.1 晶片腳位 81
5.1.2 佈局與電源規劃 82
5.2 量測考量 83
5.2.1 量測環境 83
5.2.2 高頻輸入緩衝器 84
5.2.3 高頻輸出緩衝器 85
5.3 規格比較表 86
第 6 章結論 88
6.1 結論 88
6.2 未來研究方向 89
參考文獻 90

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2024-10-22

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