應用於第五代無線通訊與X頻段之互補式金氧半導體功率放大器設計暨FR3頻段之改良型帶內全雙工電平衡雙工器之研製

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姓名

莊智皓(Chih-Hao-Chuang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於第五代無線通訊與X頻段之互補式金氧半導體功率放大器設計暨FR3頻段之改良型帶內全雙工電平衡雙工器之研製
(Design and Implementation of CMOS Power Amplifiers for 5G Wireless Communication and X-Band Applications and an Improved In-Band Full-Duplex Balanced Duplexer for the FR3 Band)

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摘要(中)

本論文介紹的第一顆晶片為使用連續B類技術之端堆疊式功率放大器，使用tsmcTM 0.18-m互補式金氧半導體設計，第二顆晶片為使用相位延遲預失真線性化器於X頻帶之差動堆疊式功率放大器，第三顆晶片為應用於FR3頻段之改良型電平衡雙工器，第二顆以及第三顆晶片皆使用tsmcTM 90-nm互補式金氧半導體設計。三顆晶片皆完成實作與量測，並針對各晶片之設計流程與量測結果進行探討。
第二章提出使用連續B類技術之端堆疊式功率放大器，此放大器採用堆疊式結構，以增加輸出電壓擺幅，從而獲得高輸出功率，有效解決了CMOS製程中因低崩潰電壓所帶來的限制。透過連續B類輸出匹配設計，以抑制二倍頻諧波量，實現了優異的功率附加效率（PAE）。其操作頻寬為4.4- 5.8 GHz，最大量測傳輸增益為23.6 dB，最大飽和輸出功率為26.2 dBm，最大功率附加效率為31.04%，而增益壓縮1-dB時之輸出功率為19.2 dBm，晶片面積為2.5 ?mm?^2(1.97 mm×1.26 mm)。
第三章提出使用相位延遲預失真線性化器於X頻帶之差動堆疊式功率放大器，透過使用磁耦合變壓器將兩個功率單元的結合，利用差動電路結構，減少寄生輸出電容、提升輸出阻抗以利匹配至系統阻抗，並結合輸入匹配磁偶和共振腔與cold-FET預失真線性化器，達成功率放大器益擴展之效果，提升電路的線性度。其操作頻寬為10-12 GHz，最大傳輸增益為12.41dB，最大輸出功率為23.43 dBm，1-dB增益壓縮點輸入功率在開啟線性化器後從4 dBm推移至9 dBm，1-dB增益壓縮點輸出功率則從17.09 dBm增加移至19.8 dBm，晶片面積為0.7645 ?mm?^2 (0.751 mm × 1.018 mm)。
第四章提出應用於FR3頻段之改良型電平衡帶內全雙工器，此設計在傳統電器平衡雙工器的設計的基礎上增加了三種可控的操作模式，使整體通訊系統能夠根據不同應用情境需求靈活調整工作狀態，增加了電路操作的彈性。其操作頻寬為9-14 GHz，當操作在平衡模式時，TX端至天線端插入損號為6.3 dB，天線端至RX端插入損號為6 dB；當操作在TX模式時，TX端至天線端插入損號為5.6 dB，天線端至RX端插入損號為7.4 dB；當操作在RX模式時，TX端至天線端插入損號為6.89 dB，天線端至RX端插入損號為5.28 dB，三種模式隔離度皆大於24 dB，晶片面積為0.486 ?mm?^2(0.697 mm× 0.697 mm)。

摘要(英)

This thesis implements three chips, each designed for specific applications in radio frequency (RF) front-end modules. The first chip is a cascode power amplifier using continuous Class-B technology, designed with the tsmcTM 0.18-μm CMOS process. The second chip is a differential cascode power amplifier incorporating a phase-delay predistortion linearizer for operation in the X-band, while the third chip is an improved balanced duplexer designed for FR3 bands. Both the second and third chips are implemented using the tsmcTM 90-nm CMOS process. All three chips have been fabricated and measured, with the design process and measurement results discussed in detail for these chips.
The second chapter presents a cascode power amplifier utilizing continuous Class-B technology. The amplifier employs a stacked structure to enhance output swing, enabling higher output power and effectively addressing the limitations imposed by the low breakdown voltage of CMOS technology. By incorporating continuous Class-B output matching design, the second-harmonic distortion is suppressed, achieving excellent power-added efficiency (PAE). This amplifier operates over a frequency range of 4.4–5.8 GHz, with a maximum measured gain of 23.6 dB, a maximum saturated output power of 26.2 dBm, and a peak PAE of 31.04%. The output power at the 1-dB gain compression point (OP1dB) is 19.2 dBm. The chip area is 2.5 mm2 (1.97 mm × 1.26 mm).
The third chapter proposes a differential stacked power amplifier incorporating a phase-delay predistortion linearizer for operation in the X-band. Magnetic transformers are used to combine two power units, while a differential circuit structure reduces parasitic output capacitance and improves output impedance, facilitating matching to the system impedance. The design integrates input matching networks, magnetic coupling resonators, and the predistortion linearizer to achieve gain expansion and enhance linearity. The amplifier operates over a frequency range of 10 -12 GHz, with a maximum gain of 12.41 dB and a maximum output power of 23.43 dBm. When the linearizer is enabled, the input power at the 1-dB gain compression point (IP1dB) increases from 4 dBm to 9 dBm, and the output power at the 1-dB gain compression point (OP1dB) rises from 17.09 dBm to 19.8 dBm. The chip area is 0.7645 mm2 (0.751 mm × 1.018 mm).
The fourth chapter proposes an improved balanced duplexer for FR3 bands, building upon the traditional balanced duplexer design by introducing three controllable operating modes. These modes allow the communication system to flexibly adapt to various application scenarios, enhancing the operational versatility of the circuit. The duplexer operates over a frequency range of 9 - 14 GHz. In balanced mode, the insertion loss from the TX port to the antenna port is 6.3 dB, and the insertion loss from the antenna port to the RX port is 6 dB. In TX mode, the insertion loss from the TX port to the antenna port is 5.6 dB, and the insertion loss from the antenna port to the RX port is 7.4 dB. In RX mode, the insertion loss from the TX port to the antenna port is 6.89 dB, and the insertion loss from the antenna port to the RX port is 5.28 dB.
For all three modes, the isolation is greater than 24 dB. The chip area is 0.486 mm2 (0.697 mm × 0.697 mm).

關鍵字(中)

★ 互補式金氧半導體功
★ 功率放大器

關鍵字(英)

★ CMOS
★ Power Amplifier

論文目次

摘要 i
Abstract iii
目錄 v
圖目錄 vii
表目錄 xi
第一章緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 研究貢獻 3
1-4 章節簡介 3
第二章使用連續B類技術之端堆疊式功率放大器 4
2-1 研究現況 4
2-2 連續模式技術介紹 6
2-3 堆疊式架構介紹 10
2-4 磁耦合變壓器介紹 11
2-5 使用連續B類技術之單端堆疊式功率放大器 18
2-5-1 架構圖 18
2-5-2 電路圖 19
2-5-3 電晶體尺寸選擇 20
2-5-4 功率級與驅動級單元設計 22
2-5-5 輸出匹配網路設計 25
2-5-6 電路模擬與量測結果 25
2-5-7 結果比較與討論 29
第三章使用相位延遲預失真線性化器於X頻帶之差動堆疊式功率放大器 45
3-1 研究現況 45
3-2 差動放大器介紹 47
3-3 線性化結構簡介 49
3-3-1 傳統cold-FET預失真線性化技術介紹 50
3-3-2 相位延遲cold-FET預失真線性化技術介紹 53
3-4 相位延遲預失真線性化器於X頻帶之差動堆疊式功率放大器 56
3-4-1 電路圖 56
3-4-2 電晶體尺寸挑選 58
3-4-3 功率級單元設計 59
3-4-4 輸出匹配網路設計 60
3-4-5 輸入匹配網路設計 65
3-4-6 相位延遲cold-FET預失真線性化器設計 68
3-4-7 電路模擬與量測結果 70
3-4-8 結果比較與討論 84
第四章應用於FR3頻段之改良型電平衡雙工器 87
4-1 研究現況 87
4-2 分時雙工(TDD)、分頻雙工(FDD)、帶內全雙工(IBFD)比較 88
4-3 電氣平衡式雙工器介紹 91
4-4 改良式電平衡雙工器 93
4-4-1 架構介紹 92
4-4-2 不同模式理論分析 94
4-5 應用於FR3頻段之改良型電平衡雙工器 99
4-5-1 電路圖 100
4-5-2 相移器設計 101
4-5-3 電平衡雙工器設計 103
4-5-4 電路模擬與量測結果 105
4-5-5 結果比較與討論 108
第五章結論 110
5-1 總結 110
5-2 未來方向 111
參考文獻 112

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[51] 3GPP TR 38.820 V16.1.0 (2021-03)

指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2025-1-14

推文