具組合式資料型樣偵測器且應用於高通道衰減補償之8 Gbps半速率不歸零資料自適應等化器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：860

、訪客IP：18.116.43.130

姓名

曹育銘(Yu-Ming Tsao) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具組合式資料型樣偵測器且應用於高通道衰減補償之8 Gbps半速率不歸零資料自適應等化器
(A 8 Gbps Half-Rate NRZ Data Adaptive Equalizer for High Channel Loss Compensation with Combinational Data Pattern Detector)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2030-1-1以後開放)

摘要(中)

隨近年來資料傳輸速率不斷提升，且由於通道近似於低通濾波器的特性，使得資料經過通道後會受到嚴重的衰減，造成符碼間干擾(Inter Symbol Interference, ISI)以及訊號完整度的問題，進一步造成接收端無法將資料正確判斷，使得後方電路運作錯誤以及誤碼率的上升。等化器的作用就是補償資料受到傳輸通道造成的高頻衰減，確保資料能夠被正確的判斷出來。此外，為了使等化器能夠適用於不同的通道衰減，會將等化器中加入自適應機制，使其能根據不同的通道衰減，自動偵測並給予資料最佳化的補償量。
在自適應系統的應用上，傳統的作法會將雙端差動的資料透過差動訊號相減的方式來判斷資料的邏輯，但是當傳輸通道的衰減嚴重到一定的程度，即使資料經過連續時間線性等化器的初步補償，資料的邏輯仍無法被輕易的判斷。這會使得後方電路無法正常運作，或導致自適應系統操作異常而收斂至不正確的位置，給予資料錯誤的補償量。因此本論文提出了一個應用於高通道衰減之自適應等化器，可以靈活運用在-11.40 dB至-31.91 dB衰減的通道，並且提出一個組合式資料型樣偵測器(Combinational Data Pattern Detector, CB-DPD)，使得資料就算受到嚴重的衰減也能夠將正確的資料型樣判斷出來，並且提供給自適應逼零演算法(Zero-forcing Algorithm)使用，使資料獲得最佳化的補償。
本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS製程實現，電路操作電壓為1V，輸入資料為8 Gb/s NRZ訊號，並且利用PRBS-7進行編碼，輸入時脈的速率為4 GHz，等化器可以補償之通道衰減的範圍為-11.40 dB至-31.91 dB，並且於短通道的佈局後模擬中眼高為406.86 mV，眼寬為110.92 ps；長通道的佈局後模擬中眼高為120.61 mV，眼寬為79.38 ps。此外，本論文所提出的CB-DPD比起傳統一般的DPD，輸出的眼高增加了58.74%。整體的功率消耗為21.70 mW，其中等化器的部分為9.02 mW，佔了41.57%；自適應的部分則為12.68 mW，佔了58.43%，晶片面積為1.13 mm2，其中核心電路面積為0.079 mm2。

摘要(英)

In recent years, as data transmission rates have continuously increased, the channel′s low-pass filter characteristics have caused significant signal attenuation after transmission. This leads to inter-symbol interference (ISI) and signal integrity issues, making it difficult for the receiver to correctly interpret the data. As a result, downstream circuits may malfunction, and the bit error rate (BER) may increase. The role of an equalizer is to compensate for high-frequency attenuation caused by the transmission channel, ensuring the data can be accurately interpreted. Additionally, to adapt the equalizer to various levels of channel attenuation, an adaptive mechanism is incorporated, allowing it to automatically detect and provide optimal compensation based on the channel′s attenuation characteristics.
In traditional adaptive systems, differential data signals are typically compared to determine their logic states. However, when the transmission channel experiences severe attenuation, even after initial compensation by a continuous-time linear equalizer (CTLE), the data logic may remain difficult to discern. This can cause downstream circuits to malfunction or the adaptive system to converge to an incorrect state, leading to improper compensation.
This study proposes an adaptive equalizer for high loss channels, capable of handling attenuation ranging from -11.40 dB to -31.91 dB. It also introduces a Combinational Data Pattern Detector (CB-DPD), which can accurately identify data patterns for zero-forcing algorithm even under severe attenuation and provide the optimal compensation for the data.
The proposed design is implemented using the TSMC 90 nm (TN90GUTM) 1P9M CMOS process. The circuit operates at 1V, inupt 8 Gbps NRZ data signals encoded with PRBS7, and uses a 4 GHz clock. The equalizer compensates for channel attenuation within a range of -11.40 dB to -31.91 dB. Post-layout simulation results show an eye height of 406.86 mV and an eye width of 110.92 ps for short channels, while for long channels, the eye height is 120.61 mV and the eye width is 79.38 ps. Furthermore, the proposed CB-DPD increases the output eye height by 58.74% compared to conventional DPD.The total power consumption is 21.70 mW, with the equalizer consuming 9.02 mW (41.57%) and the adaptive system consuming 12.68 mW (58.43%). The chip area is 1.13 mm2, with a core circuit area of 0.079 mm2.

關鍵字(中)

★ 自適應等化器
★ 連續時間線性等化器
★ 前饋式等化器
★ 組合式資料型樣偵測器
★ 自我參考技術
★ 高通道衰減

關鍵字(英)

★ adaptive system
★ continuous time linear equalizer
★ CTLE
★ feed-forward equalizer
★ FFE
★ combinational data pattern detector
★ self-reference technique
★ high channel loss

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 viii
表目錄 xii
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章高速串列傳輸之訊號完整性 5
2.1 隨機二位元資料 5
2.1.1 隨機二位元資料特性 5
2.1.2 資料類型 6
2.2 傳輸線理論 7
2.2.1 傳輸線模型[8] 7
2.2.2 傳輸線損失 11
2.2.2.1 導體損失(Conuctor Loss) 11
2.2.2.2 介質損失(Dielectric Loss) 12
2.3 抖動分析 13
2.3.1 隨機抖動(RJ) 14
2.3.2 定量性抖動(DJ) 14
2.3.2.1 週期性抖動 14
2.3.2.2 工作週期失真 15
2.3.2.3 資料相關抖動 16
2.4 單一位元脈衝響應與等化器之關係[5] 16
2.5 眼圖分析 18
2.6 誤碼率(Bit Error Rate, BER) [16] 19
第3章等化器與自適應機制之背景簡介 22
3.1 等化器的種類 22
3.1.1 連續時間線性等化器(CTLE) 23
3.1.2 決策回授等化器(DFE) 24
3.1.3 前饋式等化器(FFE) 27
3.2 自適應機制的種類 28
3.2.1 頻譜平衡技術[22] 29
3.2.2 張眼顯示器[23] 30
3.2.3 最小均方演算法 31
3.2.3.1 SS-LMS之硬體實現 33
3.2.3.2 SS-LMS之使用限制 36
3.2.4 逼零演算法 37
3.3 等化器電路之文獻探討 39
3.3.1 多階數決策迴路等化器(Multi-Tap DFE) 39
3.3.2 無限脈衝響應決策回授等化器(IIR DFE) 40
3.3.3 接收端前饋式等化器(RX-FFE) 41
3.4 比較與討論 42
第4章自適應等化器之設計與實現 44
4.1 設計流程 44
4.2 電路架構 45
4.3 操作說明 46
4.3.1 等化器補償之操作分析 46
4.3.2 自適應系統之操作分析 48
4.3.3 資料型樣偵測器之操作分析 49
4.3.3.1 傳統資料型樣偵測器(Normal-DPD)[26] 49
4.3.3.2 具自我參考技術之資料型樣偵測器[30] 50
4.3.3.3 組合式資料型樣偵測器(Combinational-DPD, CB-DPD) 51
4.4 行為模擬 52
4.5 子電路設計及分析 54
4.5.1 等化器 54
4.5.1.1 連續時間線性等化器(CTLE) 54
4.5.1.2 二階前饋式等化器(2-tap FFE) 56
4.5.2 自適應系統(Adaptive System) 59
4.5.2.1 組合式資料型樣偵測器(Combinational Data Pattern Detector, CB-DPD) 60
4.5.2.2 SS-LMS演算法系統(SS-LMS Algorithm System) 65
4.5.2.3 修正型SS-LMS演算法系統(Modified SS-LMS System) 66
4.5.2.4 補償增益控制系統(Gain Control System) 67
4.5.2.5 迴路切換系統(Loop Switch System) 69
4.6 模擬結果 71
4.6.1 通道模型 71
4.6.2 佈局前模擬(Pre-layout Simulation) 73
4.6.2.1 佈局前短通道模擬(Channel Loss = -11.40 dB @ 4GHz) 73
4.6.2.2 佈局前長通道模擬(Channel Loss = -31.91 dB @ 4GHz) 75
4.6.3 佈局後模擬(Post-layout Simulation) 77
4.6.3.1 佈局後短通道模擬(Channel Loss = -11.40 dB @ 4GHz) 77
4.6.3.2 佈局後長通道模擬(Channel Loss = -31.91 dB @ 4GHz) 79
4.6.3.3 佈局後長通道模擬之Normal-DPD Mode 81
4.6.4 模擬結果統整與比較 83
4.6.4.1 佈局前模擬結果統整與比較 83
4.6.4.2 佈局後模擬結果統整與比較 85
4.6.4.3 佈局後Normal-DPD Mode與CB-DPD Mode之結果比較 87
第5章晶片佈局與量測 88
5.1 晶片佈局 88
5.1.1 腳位配置 89
5.1.2 電源配置 91
5.1.3 佈局考量 92
5.2 量測考量 93
5.2.1 設計時的量測考量 93
5.2.2 量測環境 95
5.2.3 高速輸入緩衝器[16] 96
5.2.4 高速輸出緩衝器[16] 98
5.3 規格比較表 99
第6章結論 102
6.1 結論 102
6.2 未來研究方向 103
參考文獻 104

參考文獻

[1] VESA DisplayPort Standard, Version 2.0, Jun. 2019.
[2] PCI Express Base Specification, Revision 4.0, Version 0.7, PCI-SIG, Feb. 2016.
[3] Serial ATA Specification, Revision 3.5a, SATA-IO, Mar. 2021.
[4] Universal Serial Bus 4 Specification, Version 1.0, May 2021.
[5] 孫世洋, “以符碼間干擾偵測技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2016.
[6] Behzad Razavi, Design of Integrated Circuits for Optical Communications. McGraw-Hill: Behzad Razavi, 2003.
[7] A. X. Widmer, and P. A. Franaszek, “A DC balanced, partitioned block, 8b/10b reansmission code,” IBM J. Res and Develop., vol. 27, pp. 440 451, Sep. 1983.
[8] F. T. Ulaby and U. Ravaioli, “Transmission Lines,” in Fundamentals of Applied Electromagnetics, 6th ed. United Kingdom: Pearson, 2015, ch. 2, pp. 62-134.
[9] J. C. Rautio and V. Demir, "Microstrip conductor loss models for electromagnetic analysis," in IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 3, pp. 915 921, March 2003.
[10] Tektronix, “時序水平抖動的認識和特性分析”. Available: https://www.tek.com/tw/solutions/application/jitter-measurement-and-timing-analysis.
[11] B. Razavi, “Noise,” in Design of Analog CMOS Integrated Circuits, 2nd ed. New York, NY, USA: McGraw-Hill, 2017, ch. 7, pp. 201-239.
[12] Agilent Technologies, “Jitter Fundamentals: Agilent 81250 ParBERT Jitter Injection and Analysis Capabilities,” Application Note: 5988-9756EN, July 17, 2003.
[13] Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,” 2008.
[14] Y. Wu, “An improved statistical analysis method for duty cycle distortion jitter analysis,” in Proc. IEEE International Symposium on Consumer Electronics (ISCE), Jun. 2013, pp. 31-32.
[15] N. Na, D. M. Dreps and J. A. Hejase, “DC wander effect of DC blocking capacitors on PCIe Gen3 signal integrity,” in Proc. IEEE 63rd Electronic Components and Technology Conference, May 2013, pp. 2063-2068.
[16] 黃清和, “具可補償19-40 dB通道衰減之20 Gbps接收端自適應等化器,” 碩士論文, 國立中央大學, 2022.
[17] S Choi, S Hwang, and K. Jeong, "A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method," in IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 419-425, March 2004.
[18] J. W. Jung and B. Razavi, “A 25 Gb/s 5.8 mW CMOS equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515-526, Feb. 2015.
[19] A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno and D. Friedman, “A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3220–3231, Dec. 2012.
[20] K. -Y. Chen, W. -Y. Chen and S. -I. Liu, “A 0.31-pJ/bit 20-Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40-nm-LP CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 64, no. 11, pp. 1282-1286, Nov. 2017.
[21] 王遠, “具接收端前饋式等化器補償之10 Gb/s 全速率接收端電路,” 碩士論文, 國立中央大學, 2023.
[22] J. Lee, “A 20-Gb/s adaptive equalizer in 0.13-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011, Sep. 2007.
[23] H. Won et al., “A 28-Gb/s receiver with self-contained adaptive equalization andsampling point control using stochastic sigma-tracking eye-opening monitor,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 64, no. 3, pp. 664-674, March 2017.
[24] S. Haykin, “Wiener Filters,” in Adaptive Filter Theory, 5th ed., United Kingdom: Pearson, 2012, ch. 2, pp. 90-122.
[25] Y. Hidaka, W. Gai, T. Horie, J. H. Jiang, Y. Koyanagi and H. Osone, "A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control," in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3547-3559, Dec. 2009.
[26] 陳俊諺, “以逼零演算法實現無外部校正之單一自適應系統之5 Gbps全速率連續時間線性等化器與決策回授等化器,” 碩士論文, 國立中央大學, 2018.
[27] J. Im et al., "A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET," in IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3486-3502, Dec. 2017.
[28] S. Shahramian, B. Dehlaghi and A. Chan Carusone, "Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5 μs," in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 3192-3203, Dec. 2016.
[29] A. Agrawal, J. F. Bulzacchelli, T. O. Dickson, Y. Liu, J. A. Tierno and D. J. Friedman, "A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 3220-3231, Dec. 2012.
[30] S. Kim, J. Sim, H. Park, Y. Choi, J. Choi and C. Kim, "A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 1, pp. 101-105, Jan. 2023.
[31] D. Wang, Y. Zhao, Q. Yao, Y. Cao, B. Lian and H. Zhang, "Electrical simulation of gold bonding wire with different parameters," 2015 16th International Conference on Electronic Packaging Technology (ICEPT), Changsha, China, 2015, pp. 1329-1333.
[32] B. Zhang et al., "A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 3089-3100, Dec. 2015.
[33] Y. Frans et al., "A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET," in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1101-1110, April 2017.
[34] A. Roshan-Zamir et al., "A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 3, pp. 672-684, March 2019.
[35] J. Lee, K. Lee, H. Kim, B. Kim, K. Park and D. -K. Jeong, "A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference," in IEEE Journal of Solid-State Circuits, vol. 55, no. 8, pp. 2186-2195, Aug. 2020.
[36] B. Ye et al., "A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 58, no. 1, pp. 19-29, Jan. 2023.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2025-1-16

推文