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姓名	陳崇維(Chong-Wei Chen)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	新式雙電晶體多鐵電電容非揮發式三態內容電址記憶體矩陣之研製與特性分析 (Fabrication and Characterization of Novel 2-Transistor-n-Ferroelectric-Capacitor Non-volatile Ternary Content Address Memory Array)
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摘要(中)	在大數據時代中，如何以高速且更效率的搜尋比對極大量資料已是無法迴避的問題，此時三態內容定址記憶體(Ternary Content Addressable Memories, TCAM)，已成不可或缺的重要角色，TCAM因其擁有“Care”與“Don’t care”的功能，能夠適時的免去不必要比對操作，提高搜尋與比對的功效。對於當前基於SRAM電路所設計的揮發性TCAM，存在著較高能耗且單位面積儲存密度低的問題，所以研究利用非揮發性記憶體發展出非揮發性三態內容定址記憶體(Non-volatile Ternary Content Addressable Memories, nv-TCAM)已是必由之逕。 本篇論文利用鐵電電容下電極連接在電晶體閘極端的鐵電閘控電晶體(Ferro-gated MOSFET)設計出2T32C nv-TCAM的架構，該單元電路由一個Control-MOSFET、一個Data-MOSFET和32個金屬-鐵電層-金屬電容(MFM)組成；利用鐵電電容的極化特性改變MOSFET的通道狀態用以控制“Care”與“Don’t care”以及儲存資料。此單元架構中僅使用到兩個電晶體，並透過3D堆疊將鐵電電容以每層2個的方式堆疊16層在電晶體上，提高儲存密度並大幅降低操作功耗。此架構中的鐵電電容是利用埃層級的鐵電材料堆疊在金屬層之中，在實驗結果中，發現其擁有超寬的記憶窗口(4.94V)以及5×10??4的開關比，且每個儲存單元能夠擁有8級的儲存狀態。此外，在性能方面，搜尋時的功耗僅為9.6 μW/b，並且搜尋速度為4.5ns，每個儲存單元的耐久度(Endurance)達到1011次循環，且預測在87.6℃的環境下能達到10年的資料保存時間(Retention)。該設計改善傳統基於SRAM的TCAM 資料易失性的問題，且鐵電電容整合在CMOS製程當中，省下更多的功耗並提高儲存密度，且利用鐵電材料的特性達到多位元儲存狀態的效果，在未來對於搜尋技術上提供一個相當具有競爭力的解決方案。
摘要(英)	In the age of big data, the challenge of efficient and rapid searching and comparing vast amounts of data has become unavoidable. At this point, Ternary Content Addressable Memories (TCAM) have emerged as an indispensable technology. TCAM, with their ability to handle both “Care” and “Don’t care” states, can effectively eliminate unnecessary comparison operations, significantly enhancing efficiency in search and comparison tasks. However, contemporary volatile TCAM, which are primarily based on SRAM circuits, face challenges such as high power consumption and low storage density per unit area. As a result, researchers have begun exploring the development of Non-volatile Ternary Content Addressable Memories (nv-TCAM) utilizing non-volatile memory technologies. This paper presents a 2T32C nv-TCAM architecture designed using a Ferro-gated MOSFET, where the bottom electrode of the ferroelectric capacitor is connected to the gate terminal of the transistor. The polarization characteristics of the ferroelectric capacitor are utilized to modulate the MOSFET channel state, enabling control over the "Care" and "Don′t care" states, as well as data storage. Notably, the ferroelectric capacitor is constructed using angstrom-level ferroelectric materials stacked within the metal layers. Experimental results show that this design achieves a memory window of 4.94V, a switching ratio of 5×10?, and 8-level storage states per memory cell. In terms of performance, the power consumption during search operations is as low as 9.6 μW/b, with a fast search speed of 4.5 ns. Each memory cell demonstrates an endurance of up to 1011 cycles and a data retention time of 10 years at 87.6°C. This design resolves the data volatility issues of traditional SRAM-based TCAMs. By integrating ferroelectric capacitors into CMOS fabrication processes, it significantly reduces power consumption and improves storage density. Additionally, the unique properties of ferroelectric materials enable multi-bit storage states, offering a highly competitive solution for future search technology advancements.
關鍵字(中)	★ 非揮發性三態內容定址記憶體 ★ 鐵電電容 ★ 鐵電閘控電晶體	關鍵字(英)	★ Non-volatile Ternary Content Addressable Memories ★ Ferro-gated MOSFET ★ Ferroelectric capacitor
論文目次	摘要 I Abstract II 致謝 III 圖目錄 VI 表目錄 VIII 一、導論 1 1.1背景 1 1.2研究動機 2 1.3論文架構 2 二、鐵電記憶體介紹與應用 5 2.1鐵電材料介紹 5 2.2鐵電隨機存取記憶體(Ferroelectric Random-Access Memory, FeRAM) 6 2.3鐵電穿隧接面記憶體(Ferroelectric Tunnel Junction, FTJ) 7 2.4鐵電場效電晶體(Ferroelectric Field-Effect Transistor, FeFET) 8 2.5鐵電閘控電晶體(Ferro-gated MOSFET) 9 三、三態內容定址記憶體(TCAM)的介紹 19 3.1 CAM與TCAM之介紹 19 3.2基於SRAM之TCAM 20 3.3基於RRAM之nv-TCAM 21 3.4基於Ferro-gated MOSFET之nv-TCAM 22 四、實驗架構介紹(2T32C nv-TCAM) 28 4.1記憶體陣列架構 28 4.2元件製備 28 4.3實驗操作方式 30 4.4實驗設置 31 五、實驗結果與討論 42 5.1 2T32C nv-TCAM基本電性量測 42 5.2 2T32C nv-TCAM性能表現 42 5.3 2T32C nv-TCAM可靠度測試 43 六、結論 59 參考文獻 61
參考文獻	[1] P. Sharma, R. Anusha, K. Bharath, J. K. Gulati, P. K. Walia and S. J. Darak, "Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell," 2016 20th International Symposium on VLSI Design and Test (VDAT), Guwahati, India, 2016, pp. 342-343, doi: 10.1109/ISVDAT.2016.8064899. [2] K. L. V. Ramana Kumari, M. Asha Rani, N. Balaji, S. Kotha and M. M. Kota, "Power Optimization Analysis of Different Sram Cells Using Transistor Stacking Technique," 2021 IEEE 8th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), Dehradun, India, 2021, pp. 385-390, doi: 10.1109/UPCON52273.2021.9667583. [3] T. Rim, K. Che, S. Kwon, J. S. Lee, J. Oh, H. Ban, Jooyoung Lee, "Enhanced DRAM Single Bit Characteristics from Process Control of Chlorine," 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2023, pp. 782-785, doi: 10.1109/IRPS48203.2023.10118042. [4] R. Karam, R. Puri, S. Ghosh and S. Bhunia, "Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories," in Proceedings of the IEEE, vol. 103, no. 8, pp. 1311-1330, Aug. 2015, doi: 10.1109/JPROC.2015.2434888. [5] H. Kim and Y. Kim, "Binary Content-Addressable Memory System using Nanoelectromechanical Memory Switch," 2020 International SoC Design Conference (ISOCC), Yeosu, Korea (South), 2020, pp. 270-271, doi: 10.1109/ISOCC50952.2020.9332913. [6] S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura and T. Kawahara, "A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router," in IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 853-861, April 2005, doi: 10.1109/JSSC.2005.845554. [7] Z. Ullah, M. K. Jaiswal and R. C. C. Cheung, "Z-TCAM: An SRAM-based Architecture for TCAM," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 2, pp. 402-406, Feb. 2015, doi: 10.1109/TVLSI.2014.2309350. [8] Wang Guo, M. Bardi, Pengbo Yu and Jingjing Wu, "Research on switch address lookup table based on TCAM," International Conference on Cyberspace Technology (CCT 2014), Beijing, 2014, pp. 415-419, doi: 10.1049/cp.2014.1379. [9] A. Shaban, S. Ahmad, N. Alam and M. Hasan, "Compact and Reliable Low Power Non-Volatile TCAM Cell," 2018 8th International Symposium on Embedded Computing and System Design (ISED), Cochin, India, 2018, pp. 100-104, doi: 10.1109/ISED.2018.8704013. [10] B. Govoreanu, A. Ajaykumar, H. Lipowicz, Y.-Y. Chen, J.-c. Liu, R. Degraeve, L. Zhang, and S. Clima, and L. Goux, and I.P. Radu, and A. Fantini, and N. Raghavan, and G.-S. Kar, and W. Kim, and A. Redolfi, and D.J. Wouters, and L. Altimime, and M. Jurczak, "Performance and reliability of Ultra-Thin HfO2-based RRAM (UTO-RRAM)," 2013 5th IEEE International Memory Workshop, Monterey, CA, USA, 2013, pp. 48-51, doi: 10.1109/IMW.2013.6582095. [11] M. Kumar, M. -H. Wu, T. -H. Hou and M. Suri, "CMOS-RRAM Based Non-Volatile Ternary Content Addressable Memory (nvTCAM)," in IEEE Transactions on Nanotechnology, vol. 23, pp. 203-207, 2024, doi: 10.1109/TNANO.2024.3360312. [12] D. Takashima, "Overview of FeRAMs: Trends and perspectives," 2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding, Shanghai, China, 2011, pp. 36-41, doi: 10.1109/NVMTS.2011.6137107. [13] S. Sulaiman, H. M. Nadzar and Z. Awang, "Characterization of PZT and PNZT thin films for monolithic microwave integrated circuit applications," TENCON 2011 - 2011 IEEE Region 10 Conference, Bali, Indonesia, 2011, pp. 1235-1239, doi: 10.1109/TENCON.2011.6129003. [14] U. Celano and Y. H. Chen and A. Minj and K. Banerjee and N. Ronchi and S. McMitchell and P. Van Marcke and P. Favia and T. L. Wu and B. Kaczer and G. Van den Bosch and J. Van Houdt and P. van der Heide, "Probing the Evolution of Electrically Active Defects in Doped Ferroelectric HfO2 during Wake-Up and Fatigue," 2020 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 2020, pp. 144-145, doi: 10.1109/VLSITechnology18217.2020.9265098. [15] M. Pesic, Franz P. G. Fengler, S. Slesazeck, U. Schroeder, T. Mikolajick, L. Larcher, A. Padovani, "Root cause of degradation in novel HfO2-based ferroelectric memories," 2016 IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, 2016, pp. MY-3-1-MY-3-5, doi: 10.1109/IRPS.2016.7574619. [16] C. Sun, Q. Kong, G. Liu, D. Zhang, L. Jiao, X. L. Wang, J. Zhang, and H. W. Xu, Y. Feng, R. Shao, and Y. Chen, and X. Gong, "Understanding Bias Stress-Induced Instabilities in ALD-Deposited ZnO FeFETs Featuring HZO-Al2O3-HZO Ferroelectric Stack," in IEEE Electron Device Letters, vol. 45, no. 11, pp. 2122-2125, Nov. 2024, doi: 10.1109/LED.2024.3462933. [17] S. -C. Chang and U. E. Avci, "Hafnium-based FeRAM for Next-generation High-speed and High-Density Embedded Memory," 2022 IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, 2022, pp. 87-88, doi: 10.1109/SNW56633.2022.9889012. [18] J. Okuno, T. Kunihiro, K. Konishi, H. Maemura, Y. Shuto, F. Sugaya, and M. Materano, T. Ali, M. Lederer, K. Kuehnel, K.Seidel, U. Schroeder, T. Mikolajick, M. Tsukamoto, T. Umebayashi, "High-Endurance and Low-Voltage operation of 1T1C FeRAM Arrays for Nonvolatile Memory Application," 2021 IEEE International Memory Workshop (IMW), Dresden, Germany, 2021, pp. 44-46, doi: 10.1109/IMW51353.2021.9439595. [19] M. Yamaguchi, S. Fujii, K. Ota and M. Saitoh, "Breakdown Lifetime Analysis of HfO2-based Ferroelectric Tunnel Junction (FTJ) Memory for In-Memory Reinforcement Learning," 2020 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 2020, pp. 459-464, doi: 10.1109/IRPS45951.2020.9129314. [20] J. -Y. Lee and F.-S. Chang, K.-Y. Hsiang, P.-H. Chen, Z.-F. Luo, Z.-X. Li, J.-H. Tsai, C. W. Liu, M. H. Lee, "3D Stackable Vertical Ferroelectric Tunneling Junction (V-FTJ) with on/off Ratio 1500x, Applicable Cell Current, Self-Rectifying Ratio 1000x, Robust Endurance of 10? Cycles, Multilevel and Demonstrated Macro Operation Toward High-Density BEOL NVMs," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 459-460, doi: 10.23919/VLSITechnologyandCir57934.2023.10185163. [21] M. Abuwasib, H. Lee, P. Sharma, C. -B. Eom, A. Gruverman and U. Singisetti, "CMOS compatible integrated ferroelectric tunnel junctions (FTJ)," 2015 73rd Annual Device Research Conference (DRC), Columbus, OH, USA, 2015, pp. 45-46, doi: 10.1109/DRC.2015.7175545. [22] P. Duhan , T. Ali, P. Khedgarkar, K. Kuhnel, M. Czernohorsky, M. Rudolph, R. Hoffmann, A. Sunbul, D. Lehninger, P. Schramm, T. Kampfe, K.Seidel, "Endurance Study of Silicon-Doped Hafnium Oxide (HSO) and Zirconium-Doped Hafnium Oxide (HZO)-Based FeFET Memory," in IEEE Transactions on Electron Devices, vol. 70, no. 11, pp. 5645-5650, Nov. 2023, doi: 10.1109/TED.2023.3316138. [23] X. Li, Y. Yuan, C. J. Jin, X. Z. Li, X. Yu, B. Chen, C. Ran, G. Han, "Interface Engineering for Performance and Reliability Optimization of Hf0.5Zr0.5O2 FeFETs: Device Integration and Electrical Characterization," 2024 IEEE International Conference on IC Design and Technology (ICICDT), Singapore, Singapore, 2024, pp. 115-118, doi: 10.1109/ICICDT63592.2024.10717818. [24] F. Wei, X. Cui, S. Zhang and X. Zhang, "An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 4, pp. 2329-2333, April 2024, doi: 10.1109/TCSII.2023.3337119. [25] G. Surekha, N. Balaji and Y. Padma Sai, "A Low Power Binary CAM using 7T SRAM cell with increased substrate bias," 2021 2nd International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, 2021, pp. 691-695, doi: 10.1109/ICOSEC51865.2021.9591858. [26] S. D. Kumar and N. M. Sk, "A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic," 2015 28th International Conference on VLSI Design, Bangalore, India, 2015, pp. 316-320, doi: 10.1109/VLSID.2015.99. [27] S. Jeloka, N. B. Akesh, D. Sylvester and D. Blaauw, "A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory," in IEEE Journal of Solid-State Circuits, vol. 51, no. 4, pp. 1009-1021, April 2016, doi: 10.1109/JSSC.2016.2515510. [28] Z. Wang, P. Li, Z. Wang, S. Xing, X. Fan and Y. Zhang, "A Novel RRAM-Based TCAM Search Array," 2024 Conference of Science and Technology for Integrated Circuits (CSTIC), Shanghai, China, 2024, pp. 168-170, doi: 10.1109/CSTIC61820.2024.10531948. [29] L. Zheng, S. Shin, S. Lloyd, M. Gokhale, K. Kim and S. -M. Kang, "RRAM-based TCAMs for pattern search," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, 2016, pp. 1382-1385, doi: 10.1109/ISCAS.2016.7527507. [30] E. R. Hsieh, Y. L. Hsueh, R. Q. Lin, Y. X. Huang, P. J. Hou, K. H. Chang, T. H. Shen, Y. H. Li, R. Y. Lyu, "A Nonvolatile Ternary-Content-Addressable- Memory Comprising Resistive-Gate Field-Effect Transistors," in IEEE Electron Device Letters, vol. 44, no. 8, pp. 1292-1295, Aug. 2023, doi: 10.1109/LED.2023.3289179. [31] Y. L. Hsueh, R. Q. Lin, Y. X. Huang, Y. H. Lin, K. H. Chang, T. H. Shen, E. R. Hsieh, S. Wong, "A New 1C1T1R nv-TCAM with Simultaneously Hybrid Ferroelectricity and Memristor Layers Feasible for Ultra-highly-dense and High-performance In-memory-searching," 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 171-173, doi: 10.1109/EDTM58488.2024.10512294. [32] M. -F. Chang, L. Y. Huang, W. Z. Lin, Y. N. Chiang, C. C. Kuo, C. H. Chuang, K. H. Yang, H. J. Tsai, T. F. Chen, S. S. Sheu, "A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing," in IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2786-2798, Nov. 2016, doi: 10.1109/JSSC.2016.2602218. [33] M. -F. Chang, C. C. Lin, Albert Lee, Y. N. Chiang, C. C. Kuo, G. H. Yang, H. J. Tsai, T. F. Chen, S. S. Sheu, "A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing," in IEEE Journal of Solid-State Circuits, vol. 52, no. 6, pp. 1664-1679, June 2017, doi: 10.1109/JSSC.2017.2681458. [34] D. R. B. Ly, J-P. Noel, B. Giraud, P. Royer, E. Esmanhotto, N. Castellani, T. Dalgaty, J-F. Nodin, C. Fenouillet-Beranger, E. Nowak, E. Vianello, "Novel 1T2R1T RRAM-based Ternary Content Addressable Memory for Large Scale Pattern Recognition," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 35.5.1-35.5.4, doi: 10.1109/IEDM19573.2019.8993621. [35] C. Marchand, I. O’Connor, M. Cantan, E. T. Breyer, S. Slesazeck and T. Mikolajick, "A FeFET-Based Hybrid Memory Accessible by Content and by Address," in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 8, no. 1, pp. 19-26, June 2022, doi: 10.1109/JXCDC.2022.3168057. [36] S. Lim, D. H. Ko, S. K. Kim and S. -O. Jung, "Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 2, pp. 806-818, Feb. 2023, doi: 10.1109/TCSI.2022.3222383.
指導教授	謝易叡(E-Ray Hsieh)	審核日期	2025-1-17
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