應用於光耦合隔離系統發送端之動態縮放式 類比數位轉換器

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姓名

張博翔(Po-Hsiang Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於光耦合隔離系統發送端之動態縮放式類比數位轉換器
(A Design of Dynamic Zoom ADC for Optical Coupling Isolation Applications)

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摘要(中)

隨著現代科技的發展，人類目前正處於工業4.0，即第四次工業革命，透過智慧控制、AI演算法監測和機器人等實體設備為自動化系統和監控技術帶來革新。在當下的工業控制產品，如交流伺服馬達控制器、工業自動化逆變器以及用於再生能源的功率調節器，追求效率的同時對精準度的要求也近一步提升。在工業控制中，精確的取樣來自感測器的訊號是整體系統的關鍵部分。而在工業的應用方面，其設備的運作環境經常會工作在較危險的電壓範圍，因此量測系統除了追求更高的精準度外還需要確保本身的安全性及可靠度，正因其較嚴苛的運行條件，使隔離器被廣泛的應用於工業控制中，以此來保護人員安全和鄰近的電子設備。
本論文實現一個應用於光耦合隔離系統發送端之高解析度動態縮放式類比數位轉換器(Dynamic Zoom Analog-to-Digital Converter, Dynamic Zoom ADC)，其架構主要包含一個5位元非同步連續漸進式類比數位轉換器(Successive-Approximation Register ADC, SAR ADC)、二階三角積分調變器(Sigma-Delta Modulator, SDM)、資料加權平均(Data-Weighted Averaging, DWA)，SAR ADC選用非同步時脈架構可在每個取樣週期對輸入訊號進行追蹤並透過超量程(Over-ranging)與數位類比轉換器(Digital-to-Analog Converter, DAC)更新參考電壓，減少SDM發散機率的同時提升訊號雜訊比(Signal-to-Noise, SNR)與輸入訊號頻寬，SDM對SAR ADC初步量化的結果進一步完成雜訊整形(Noise-Shaping)，藉此提升轉換解析度，DWA則是負責通過電容校正技術避免製程變異造成整體Zoom ADC的SNR劣化。
本論文晶片採用台積電0.18μm CMOS 1P6M製程，在包含ESD保護電路下的晶片面積為1.44 mm2，電源供應電壓為1.8V，整體電路功耗約為1.7 mW，電路頻寬為20 kHz，電路最高取樣頻率可達10.24 MHz，超取樣率為256，在開關電容架構下實現解析度為18位元。

摘要(英)

With the advancement of modern technology, humanity is now in the era of Industry 4.0, also known as the Fourth Industrial Revolution, which introduces innovations to automation systems and monitoring technologies through intelligent control, AI algorithms, and physical equipment such as robots. In contemporary industrial control products, such as AC servo motor controllers, industrial automation inverters, and power regulators for renewable energy, there is a growing demand for both higher efficiency and enhanced precision. In industrial control, accurate sampling of signals from sensors is a critical component of the overall system. Furthermore, industrial equipment often operates within hazardous voltage ranges, requiring measurement systems to prioritize not only precision but also safety and reliability. Due to these stringent operational conditions, isolators are widely used in industrial control to ensure personnel safety and protect nearby electronic equipment.
This thesis presents the implementation of a high-resolution, Dynamic Zoom Analog-to-Digital Converter (Dynamic Zoom ADC) for the transmitter side of an optocoupler-based isolation system. The proposed architecture mainly comprises a 5-bit asynchronous Successive Approximation ADC (SAR ADC), a second-order Sigma-Delta Modulator (SDM), and Data-Weighted Averaging (DWA). The asynchronous clocking structure of the SAR ADC enables it to track the input signal during each sampling period and update the reference voltage through over-ranging and a Digital-to-Analog Converter (DAC). This reduces the divergence probability of the SDM while enhancing the Signal-to-Noise Ratio (SNR) and input signal bandwidth. The SDM further processes the preliminary quantization results of the SAR ADC to perform noise shaping, thereby improving the conversion resolution. The DWA employs capacitor mismatch correction techniques to prevent process variations from degrading the overall SNR of the Zoom ADC.
The chip is fabricated using TSMC’s 0.18 μm CMOS 1P6M process, with a total chip area of 1.44 mm2, including ESD protection circuits. The power supply voltage is 1.8V, and the overall circuit consumes approximately 1.7 mW. The circuit bandwidth is 20 kHz, with a maximum sampling frequency of 10.24 MHz and an oversampling ratio of 256. Under the switched-capacitor architecture, the ADC achieves a resolution of 18 bits.

關鍵字(中)

★ 動態縮放式類比數位轉換器
★ 三角積分調變器
★ 連續漸進式類比數位轉換器

關鍵字(英)

★ Dynamic Zoom ADC
★ Sigma-Delta Modulator
★ Successive-Approximation Register ADC

論文目次

摘要 ............................................................................................................................................. i
Abstract....................................................................................................................................... ii
致謝 ........................................................................................................................................... iv
目錄 ............................................................................................................................................ v
圖目錄 ..................................................................................................................................... viii
表目錄 ....................................................................................................................................... xi
第一章緒論 .............................................................................................................................. 1
1.1 背景 1
1.2 研究動機 2
1.3 論文貢獻 4
第二章類比數位轉換器原理概論 .......................................................................................... 5
2.1 奈奎斯特與超取樣類比數位轉換器介紹 5
2.2 量化誤差與超取樣技術 7
2.3雜訊整形技術 10
2.3.1一階三角積分調變器 11
2.3.2二階三角積分調變器 13
2.3.3高階三角積分調變器 14
第三章動態縮放式類比數位轉換器概論 ............................................................................ 16
3.1 二階段類比數位轉換器介紹 16
3.2 動態縮放式類比數位轉換器架構分析 19
3.3 超量程技超量程技術術 .............................................................................................................................................................................................................................. 22
3.4 連續漸進式類比數位轉換器連續漸進式類比數位轉換器 ...................................................................................................................................................................... 25
3.4.1 同步時脈同步時脈 ................................................................................................................................................................................................................ 25
3.4.2 非同步時脈非同步時脈 ........................................................................................................................................................................................................ 28
第四章動態縮放式類比數位轉換器設計與模擬 ................................................................ 30
4.1 動態縮放式類比數位轉換器系統模擬動態縮放式類比數位轉換器系統模擬 ...................................................................................................................................... 31
4.1.1規格訂製規格訂製 .................................................................................................................................................................................................................. 31
4.1.2系統設計系統設計 .................................................................................................................................................................................................................. 32
4.2 系統非理想效應考量系統非理想效應考量 .............................................................................................................................................................................................. 34
4.2.1 運算放大器增益誤差運算放大器增益誤差 ........................................................................................................................................................................ 34
4.2.2 運算放大器增益頻寬積運算放大器增益頻寬積 ................................................................................................................................................................ 36
4.2.3 熱雜訊熱雜訊 ........................................................................................................................................................................................................................ 38
4.3 電路設計電路設計 ...................................................................................................................................................................................................................................... 41
4.3.1 非同步連續漸進式類比數位轉換器非同步連續漸進式類比數位轉換器 ........................................................................................................................ 43
4.3.2 運算轉導放大器運算轉導放大器 ........................................................................................................................................................................................ 45
4.3.3 靴帶式開關電路靴帶式開關電路 ........................................................................................................................................................................................ 48
4.3.4 互補式開關電路互補式開關電路 ........................................................................................................................................................................................ 49
4.3.5 資料加權平均資料加權平均 ................................................................................................................................................................................................ 50
4.3.6 非重疊時脈產生器非重疊時脈產生器 ................................................................................................................................................................................ 54
4.4 佈局前模擬結果佈局前模擬結果 .............................................................................................................................................................................................................. 55
第五章晶片佈局與模擬 ........................................................................................................ 59
5.1 佈局平面圖佈局平面圖 .............................................................................................................................................................................................................................. 59
5.2 佈局後模擬結果佈局後模擬結果 .............................................................................................................................................................................................................. 61
5.3 量測考量量測考量 ...................................................................................................................................................................................................................................... 65
第六章結論與未來展望 ........................................................................................................ 67
6.1 文獻比較文獻比較 ...................................................................................................................................................................................................................................... 67
6.2 未來展望未來展望 ...................................................................................................................................................................................................................................... 68
參考文獻 .................................................................................................................................. 69

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指導教授

薛木添

審核日期

2025-2-25

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