通用LIB格式運用於尺寸可變的嵌入式記憶體功率模型

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：30

、訪客IP：13.58.11.68

姓名

游智嘉(Chi-Chia Yu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

通用LIB格式運用於尺寸可變的嵌入式記憶體功率模型
(A Scalable Power Modeling Approach for Embedded Memory Using LIB Format)

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 高速序列傳輸之量測技術
★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路	★ 類神經網路應用於高階功率模型之研究
★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究	★ 以回填法建立鎖相迴路之行為模型的研究
★ 高速傳輸連結網路的分析和模擬	★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法
★ 抑制同步切換雜訊之高速傳輸器	★ 以行為模型建立鎖相迴路之非理想現象的研究
★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究	★ 用於命題驗証方式的除錯協助技術之研究
★ Verilog-A語言的涵蓋率量測之研究	★ 利用類神經模型來估計電源線的電流波形之研究
★ 5.2GHz CMOS射頻接收器前端電路設計	★ 適用於OC-192收發機之頻率合成器和時脈與資料回復電路

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

摘要
在這篇論文裡，我們發展兩種方法改進記憶功率估計的準確。我們提升的記憶體功率模型能不僅考慮記憶體的操作模式，也考慮輸入位址切換的影響和從記憶體架構中得到不同大小記憶體之間的比例因子。我們提出的方法可以有效的結合記憶體產生器產生任意大小的記憶體功率模型，無需再對不同大小的記憶體再做一次功率模型。接著提出來的Dummy Modular方法可以將我們的功率模型和商業估測功率軟體流程互相結合。實驗結果已經顯示我們的記憶功率模型的平均誤差少於5%。

摘要(英)

Abstract
In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effect and the scaling factors that use the information of physical architecture. The proposed approach is very useful to be combined with memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into commercial power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.

關鍵字(中)

★ 記憶體
★ 功率

關鍵字(英)

★ memory
★ power

論文目次

CONTENTS
Chapter 1 Introduction 1
Chapter 2 Preliminary 5
2.1 Power Consumption of CMOS Digital circuit 5
2.2 Traditional Memory Power Estimation 7
2.3 Embedded Memory Architecture 11
2.4 Linear Regression 14
2.4.1 Linear Regression 14
2.4.2 Least-Squares Regression 15
2.4.3 Correlation 15
Chapter 3 Enhanced Memory Power Modeling Using LIB Format 17
3.1 Dummy Modular Approach 19
3.2 Combine Our Model with Memory Compiler in Current EDA Flow 22
Chapter 4 Scalable Model Equations 23
4.1 Memory Core 27
4.2 Controller Circuit 28
4.3 Column/Row Decoder 29
4.4 Scalable Methodology 30
4.5 Frequency and Leakage Power 32
4.5.1 Leakage Power 32
4.5.2 Frequency 33
Chapter 5 Experimental Results 35
Chapter 6 Conclusions 41
References 42

參考文獻

References
[1] Michael Keating, Pierre Bricaud, “Reuse Methodology Manual: For System-On-A-Chip Designs”, Kluwer Academic Publishers, 2002
[2] “Library Compiler User Guide: Modeling Timing and Power Technology Libraries”, Synopsys, March 2003.
[3] Swapnajit Mittra, “Principles of Verilog PLI”, Kluwer Academic Publishers, March 1999.
[4] Amrutur, B.S.; Horowitz, M.A., “Speed and power scaling of SRAM's”, IEEE Trans. Solid-State Circuits, vol. 35, Feb. 2000 pp. 175 – 185.
[5] Evans, R.J.; Franzon, P.D., “Energy consumption modeling and optimization for SRAM's”, IEEE Trans. Solid-State Circuits, vol. 30, May 1995, pp. 571 – 579.
[6] Chinosi, M.; Zafalon, R.; Guardiani, C., “Automatic characterization and modeling of power consumption in static RAMs”, Low Power Electronics and Design, Aug. 1998.
[7] Coumeri, S.L.; Thomas, D.E., Jr., “Memory modeling for system synthesis”, IEEE Trans. On VLSI Syst., vol. 8, June 2000, pp. 327 – 334.
[8] Schmidt, E.; von Colln, G.; Kruse, L.; Theeuwen, F.; Nebel, W., “Memory Power Models for Multilevel Power Estimation and Optimization”, IEEE Trans. VLSI Syst., vol. 10, April 2002, pp. 106-109.
[9] J. Olson, I. Nedelchev, Y. Lin, A. Mauskar, and J. Sproch, “STATE DEPENDENT POWER MODELING,” US Patent # 5,838,579, 1998.
[10] “TSMC 0.25μm Process SRAM-SP-HD Generator User Manual”, Release 5.0, Artisan Comp., January 2002.
[11] Ashok K. Sharma, “Advanced Semiconductor Memories: Architectures, Designs, and Applications”, Piscataway, NJ: IEEE Press; Hoboken, NJ: Wiley-Interscience, 2003.
[12] Wen-Tsan Hsieh; Chien-Nan Jimmy Liu; Yao-Feng Wang; Yi-Fang Chiu; “An efficient power modeling approach for embedded memory using LIB format”, VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on 27-29 April 2005 Page(s):55 – 58

指導教授

劉建男(Chien-Nan Liu)

審核日期

2006-7-18

推文