DSpace collection: 期刊論文

清初漢文人心態的轉變及其對詩詞風氣的影響－以康熙十八年（1679）博學鴻儒科為考察中心

title: 清初漢文人心態的轉變及其對詩詞風氣的影響－以康熙十八年（1679）博學鴻儒科為考察中心 abstract: 摘要：滿清統治者創建王朝，入主中原的過程，是一個由武功主導走向文治主導的戰略佈局。到了博學鴻儒科的詔開，這一戰略佈局得以基本完成。康熙十八年（1679）博學鴻儒科的舉辦，不僅是吸收人才，也不僅是爭取民心（士民之心），更重要的是爭取滿清王朝統治的合法性與正當性；確切說，是滿清作為異族入主中原，秉承正統，承續法統的歷史迫切性所致；也是對已有的漢文人效忠者進行體制化、典範化，爭取漢文人對新朝法理正統的認可與遵奉；從而促使漢士人心態╱立場╱身分的轉型完成。對清初詩詞風氣的影響，主要體現在三個方面：詩詞觀念上，由「窮而後工」轉向「達而後工」；創作精神上，由「諷喻美刺」轉向「歌功頌德」；風格形態上，由「幽愁慷慨」轉向「睿藻炳然」。出版者：中央研究院中國文哲研究所出版日期： 2016-09-01 出處：中國文哲研究集刊, 2016-09 (49), p.41-81 資源來源： Chinese Electronic Periodical Services (CEPS) 識別號： ISSN: 1017-6462

Write current self-configuration scheme for MRAM yield improvement

title: Write current self-configuration scheme for MRAM yield improvement abstract: 摘要： Magnetic random access memory (MRAM) is an emerging nonvolatile memory, which is widely studied for its high speed, high density, small cell size, and almost unlimited endurance. However, for deep-submicrometer process technologies, significant variation in the MRAM cells' operating condition results in write failures in cells and reduces the production yield. Memory designers have to characterize failed MRAM chips to find a suitable current level for reconfiguring their write current, which is time consuming. In this paper, we propose an efficient operating-current search method and the corresponding built-in circuit for toggle MRAM, which can rapidly find the minimal operating current. With the built-in search circuit, an MRAM chip can dynamically configure its write current through few tester channels. The resulting chip works correctly and consumes lower power. Production yield, thus, can be increased while the test cost is greatly reduced. We also present a generator of the circuit, which determines the circuit parameters according to the memory specifications and user requirements, and automatically generates the corresponding modules. 其他題名： TVLSI 出版者： New York, NY: IEEE 出版日期： 2013-07-01 出處： IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1260-1270 資源來源： IEEE Xplore (NTUSG) 版權： 2014 INIST-CNRS 識別號： ISSN: 1063-8210 識別號： EISSN: 1557-9999 識別號： DOI: 10.1109/TVLSI.2012.2207136 識別號： CODEN: IEVSE9

RRAM defect modeling and failure analysis based on march test and a novel squeeze-search scheme

title: RRAM defect modeling and failure analysis based on march test and a novel squeeze-search scheme abstract: 摘要： The Resistive Random Access Memory (RRAM) is a new type of non-volatile memory based on the resistive memory device. Researchers are currently moving from resistive device development to memory circuit design and implementation, hoping to fabricate memory chips that can be deployed in the market in the near future. However, so far the low manufacturing yield is still a major issue. In this paper, we propose defect and fault models specific to RRAM, i.e., the Over-Forming (OF) defect and the Read-One-Disturb (R1D) fault. We then propose a March algorithm to cover these defects and faults in addition to the conventional RAM faults, which is called March C*. We also develop a novel squeeze-search scheme to identify the OF defect, which leads to the Stuck-At Fault (SAF). The proposed test algorithm is applied to a first-cut 4-Mb HfO 2 -based RRAM test chip. Results show that OF defects and R1D faults do exist in the RRAM chip. We also identify specific failure patterns from the test results, which are shown to be induced by multiple short defects between bit-lines. By identifying the defects and faults, designers and process engineers can improve the RRAM yield in a more cost-effective way. 其他題名： TC 出版者： New York: IEEE 出版日期： 2015-01-01 出處： IEEE Transactions on Computers, 2015-01, Vol.64 (1), p.180-190 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2015 識別號： ISSN: 0018-9340 識別號： EISSN: 1557-9956 識別號： DOI: 10.1109/TC.2014.12 識別號： CODEN: ITCOB4

Reactivation of spares for off-chip memory repair after die stacking in a 3-D IC with TSVs

title: Reactivation of spares for off-chip memory repair after die stacking in a 3-D IC with TSVs abstract: 摘要： Memory, especially DRAM, is one of the candidates to be considered in three-dimensional integrated circuit (3-D IC), and in particular, to be heterogeneously stacked with a system on chip (SOC) for mobile applications. Even though the memory is tested and repaired beforehand, the known good die (KGD) can become bad during the integration process. Traditional schemes may not be able to redo the repair and obtain a known good stack (KGS), let alone unused spares be reused. We propose an off-chip repair scheme to deal with the inaccessibility from outside of the memory die. Using a through silicon via (TSV) to access the redundancy control circuit (RCC), we reactivate the unused spares by overwriting their states as if the corresponding fuses are blown. Even when the row or column, which has already been repaired, is damaged again, we are able to replace it with a new spare. Our simulation using a 65 nm process technology shows that the maximum timing penalty of the off-chip repair is only 93ps, compared to the on-chip method. The area overhead is estimated to be 490 μm 2 per fuse set by using a 5 μm diameter TSV process. Most importantly, the yield improvement of a two-die stacked memory can be over 50% with yield excursion reduced to 8%. 其他題名： TCSI 出版者： New York: IEEE 出版日期： 2013-09-01 出處： IEEE transactions on circuits and systems. I, Regular papers, 2013-09, Vol.60 (9), p.2343-2351 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Sep 2013 識別號： ISSN: 1549-8328 識別號： EISSN: 1558-0806 識別號： DOI: 10.1109/TCSI.2013.2246235 識別號： CODEN: ITCSCH