DSpace community: 資訊電機學院

開發多樣化植入式醫療裝置的無線電力和雙向資料傳輸系統;Development of a Wireless Power and Bidirectional Data Transfer System for Multiple Implantable Medical Devices

title: 開發多樣化植入式醫療裝置的無線電力和雙向資料傳輸系統;Development of a Wireless Power and Bidirectional Data Transfer System for Multiple Implantable Medical Devices abstract: 植入式醫療裝置(IMD)是指透過手術植入人體的醫療裝置，早期的植入式醫療裝置作為獨立裝置運行，需要透過有線電極或是短程通訊設備溝通，對病患日常生活有著相當程度的影響。如今有多種通訊協定通過小型移動通訊裝置接收生醫訊號，並與終端機溝通將資料上傳至雲端，方便醫生隨時進行診斷與維護實現遠距醫療。本研究基於植入式醫療裝置應用，提出開發多樣化植入式醫療裝置的無線電力與雙向資料傳輸系統。本研究將整個無線傳輸系統分成發射系統與接收系統，並且將關鍵電路以晶片電路實現，製程採用TSMC 0.18 μm CMOS Technology實現。在發射系統，本研究提出11-Bits SAR ADC晶片的電源電壓1.2V，輸入電壓範圍為300mV~900mV，採樣率10kS/s。在解析度與採樣速率取得平衡，且在DNL與INL上優異的表現均低於0.5 LSB，確保ADC不會出現漏碼（missing codes），選擇非同步的架構減少時脈產生的雜訊（jitter），可透過SFDR觀察對時脈抖動的表現，78.9dBc的數值表明確實在jitter的處理上表現優異。在植入式醫療裝置的考量上，本研究ADC功耗僅為932nW對IMD幾乎可忽略不計，產生熱量遠低於組織代謝熱，∆T<0.001℃。其數據表明長時間植入不會對周圍組織產生熱損傷，加上實際ENOB有9.2 bits十分適合IMD應用。在接收系統，本研究提出升壓比較整流器電路，使用電感耦合無線電力傳輸位晶片供電，輸入訊號為振福3.3頻率2 MHz正弦波。可得到VCE在R_L=8kΩ時達89.02%，PCE在R_L=500Ω時有84.73%，最大輸出電流為5 mA，整流晶片功率消耗為12.35 mW。採用ALL-NMOS功率電晶體的整流架構避免出現寄生P-N-P-N結構，遏止因P-N-P-N結構發生latch-up，並設計保護電路以避免電晶體節點因高壓損壞。本研究提出整流器晶片電路實現，應用於2 MHz的操作頻率兼具電感耦合線圈大小與人體吸收率SAR低。5 mA的最大輸出電流適合多數植入式應用，89.02%的VCE和2.94V的穩定輸出電壓，滿足大多數供電需求。84.73%的PCE局部溫升僅0.22-0.45℃，符合ISO與IEC所規範的2℃。各項指標均顯示此設計是符合IMD應用。 ;Implantable medical devices (IMDs) are devices surgically implanted into the human body. Early IMDs functioned as stand-alone units, relying on wired electrodes or short-range communication equipment, which significantly affected patients′ daily lives. Today, various communication protocols enable small mobile devices to receive biomedical signals and communicate with terminals to upload data to the cloud, facilitating remote diagnosis and maintenance by healthcare professionals. This research, based on the application of IMDs, proposes the development of a wireless power and bidirectional data transfer system for multiple implantable medical devices. This research divides the wireless transfer system into a transmitter system and a receiver system. TSMC′s 0.18 μm CMOS technology is employed to realize the key circuits: ADC and rectifier. This study proposes a 10kS/s, 11-bit SAR ADC designed for transmitter systems. Powered by a 1.2 V supply, the device handles input signals ranging from 300 mV to 900 mV. A balance is achieved between medium resolution and medium sampling rate, with excellent performance in both DNL and INL, each below 0.5 LSB, ensuring no missing codes. An asynchronous architecture is employed to reduce clock jitter, and the effectiveness in handling clock jitter is demonstrated by an SFDR value of 78.9dBc, indicating excellent jitter tolerance. Considering implantable medical devices, the ADC’s power consumption is only 932 nW, which is negligible for IMDs, and the heat generated is far lower than tissue metabolic heat (∆T<0.001℃). These data indicate that long-term implantation will not cause thermal damage to surrounding tissues, and the actual ENOB of 9.2 bits is well suited for IMD applications. This study proposes a boost-comparator rectifier circuit for the receiver system, powered by an inductive coupling wireless power transfer. An inductive coupling wireless power transfer system generates the input signal, which is characterized as a 2 MHz sine wave with a 3.3 V amplitude. The VCE reaches 89.02% at a load resistance (R_L) of 8 kΩ, while the PCE attains 84.73% at R_L=500Ω. The maximum output current is 5 mA, and the rectifier chip′s power consumption is 12.35 mW. Rectifier architecture with all-NMOS power transistors is employed to eliminate parasitic P-N-P-N structures, thereby preventing latch-up. This study proposes a self-bootstrapping architecture to improve the insufficient charging efficiency of NMOS devices and incorporates protection circuits to prevent transistor node breakdown from high voltage. The proposed rectifier circuit operates at 2 MHz, balancing the size of the inductive coupling coil and the specific absorption rate (SAR) in the human body. The maximum output current of 5 mA is suitable for most implantable applications. The VCE of 89.02% and a stable output voltage of 2.94 V meet typical power supply requirements. The PCE results in a local temperature rise of only 0.22–0.45°C, well within the 2°C limit specified by ISO and IEC standards. All performance indicators demonstrate that this design complies with IMD application requirements.

高功率密度氮化鎵基三相飛跨電容多層級轉換器之建模與控制;Modeling and Control of High-Power-Density GaN-Based Three-Phase Flying Capacitor Multilevel Converters

title: 高功率密度氮化鎵基三相飛跨電容多層級轉換器之建模與控制;Modeling and Control of High-Power-Density GaN-Based Three-Phase Flying Capacitor Multilevel Converters abstract: 本論文探討採用飛跨電容多電平拓樸之高功率密度三相 AC–DC 轉換器在設計與控制上的挑戰。由於電容相較於電感具有更高的能量密度，加上低電壓開關元件具備更佳的性能指標，本研究以飛跨電容多電平轉換器作為同時實現高效率、高功率密度以及降低被動元件體積的可行方案。然而，在實際飛跨電容多電平應用中，一項關鍵問題是如何維持飛跨電容電壓平衡，尤其在直流母線電壓變動或電網不平衡的情況下更形困難。傳統主動平衡方法需大量飛跨電容電壓感測，不僅提高系統成本與複雜度，也限制多電平轉換器於高電平數時的可擴展性。為解決上述問題，本論文提出三項主要貢獻。首先，發展虛擬磁通–電壓調變直接功率控制策略，使三相飛跨電容多電平整流器無需電網電壓感測器即可運作。藉由將系統轉換為線性非時變模型，該方法可在電網平衡與不平衡條件下皆可維持強健控制。其次，本論文提出基於滑模觀測器之飛跨電容電壓無感測主動平衡策略。利用互連系統模型設計超扭轉觀測器，以精準估測飛電容電壓並取代直接量測，並透過李雅普諾夫穩定性分析保證觀測誤差的收斂性。此方法避免傳統方法對電容特性的限制性假設，並具備對參數變動與電網不平衡的強健性。第三，本論文提出高功率密度三相七電平飛跨電容多電平功因校正前端整流器之設計，包含依多電平橋臂縮放定律決定適當電平數、硬體設計、損耗分析，以及推廣至一般 N 電平架構。本論文提出的控制策略與無電壓感測主動平衡方法，經由三相七電平飛跨電容多電平轉換器的完整模擬與實驗驗證。結果顯示所提出之技術具備可行性、強健性與卓越性能，適用於新一代高功率密度整流器，例如電動車快速充電與資料中心電源等應用。;This thesis addresses the design and control challenges of high-power-density three-phase AC–DC conversion using a Flying Capacitor Multilevel (FCML) converter topology. Motivated by the superior energy density of capacitors relative to inductors and the favorable figures-of-merit (FOM) of low-voltage switching devices, the FCML converter is investigated as a means to simultaneously achieve high efficiency, high power density, and reduced passive component volume. A key obstacle in practical FCML implementations is the need to maintain balanced flying capacitor voltages, especially under conditions of varying DC-link voltage or unbalanced grid operation. Conventional active balancing methods rely on extensive capacitor-voltage sensing, which increases system cost and complexity and limits scalability in high-level converters. To address these challenges, this thesis makes three main contributions. First, a virtual flux voltage modulated direct power control (VF-VMDPC) scheme is developed to regulate a three-phase FCML rectifier without requiring grid-voltage sensors. By transforming the system into a linear time-invariant form, the proposed method enables robust control under both balanced and unbalanced grid conditions. Second, a flying capacitor voltage sensorless control strategy is proposed using the interconnected system model for three-phase FCML based on a sliding mode observer (SMO) with active balancing method, eliminate the need for direct sensing. Then, a super-twisting observer (STO) is designed to accurately estimate flying capacitor voltages, reduces chattering, and Lyapunov stability analysis is utilized to guarantee convergence. The method avoids restrictive assumptions on capacitor characteristics and achieves robustness to parameter variations and grid imbalance. Third, the thesis presents the design of a high-power-density three-phase 7-level FCML PFC front-end rectifier. The appropriate number of levels is determined using multilevel bridge-leg scaling laws, followed by de-tailed hardware design, loss analysis. The proposed control VF-VMDPC strategy and observer-based sensorless balancing approach are validated through comprehensive simulations and experimental implementation of three-phase 7-level FCML converter. The results confirm the feasibility, robustness, and performance advantages of the proposed techniques, demonstrating their suitability for next-generation high-power-density rectifiers used in applications such as EV fast chargers and data-center power delivery systems.

寬能隙氧化物二極體與N型MOS電晶體之研究;The Research on Wide-Bandgap Oxide Diodes and N-type MOS Transistors

title: 寬能隙氧化物二極體與N型MOS電晶體之研究;The Research on Wide-Bandgap Oxide Diodes and N-type MOS Transistors abstract: 隨著全球暖化與能源短缺，特別是人工智慧 (AI) 帶來的電力需求激增，如何提升電子元件的能源使用效率，已成為現代功率元件領域的重要課題。其中，金屬氧化物半導體場效電晶體 (MOSFET) 是功率管理系統中的核心元件。本研究旨在探討寬能隙氧化物材料——氧化鋅 (ZnO) 與氧化鎵 (Ga2O3) 於金屬氧化物半導體元件開發與整合的可行性。在材料製備方面，本研究聚焦於實現氧化鋅穩定 p 型摻雜的技術。選用五族元素磷 (P) 作為摻雜劑，並透過冷壓與兩階段高溫燒結技術製備 p 型氧化鋅塊材。研究中利用 X 光繞射儀 (XRD) 與拉曼光譜分析粉體結晶性，並透過掃描式電子顯微鏡 (SEM) 與能量散射光譜儀 (EDS) 觀察形貌與元素比例。實驗結果顯示，在 50°C 至 200°C 的環境下，摻雜濃度為 0.4at% 的磷原子能展現最穩定的 p 型半導體特性及最佳的摻雜效果。在燒結氣氛研究中，真空環境有助於氧化鋅塊材維持穩定的 p 型特性與較低電阻率；而富氧環境則能有效抑制 n 型本徵缺陷，適合製備金屬氧化物半導體場效電晶體之基板。在元件製作方面，本研究成功於 p 型氧化鋅塊材基板上製備 n 型氧化鋅 MOSFET 元件。此外，針對具備寬能隙特性的第四代半導體氧化鎵，本研究利用液態金屬剝離轉印法所製備出的超薄氧化鎵作為通道材料，開發出 n 型氧化鎵 MOSFET 元件。期望透過對氧化鋅材料 p 型摻雜與電晶體製程參數的最佳化，為高效能功率管理與能源電子系統提供可行的技術方案。;With the challenges of global warming, energy shortages, and the surging demand for electricity in artificial intelligence, improving the energy efficiency of electronic components has become a critical research topic in the field of modern power devices. Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are core components in these power management systems. This study explores the feasibility of utilizing wide-bandgap oxide materials—zinc oxide (ZnO) and gallium oxide (Ga2O3)—for the development of high-performance MOSFETs. In terms of material preparation, this study focuses on achieving stable p-type doping of zinc oxide. Phosphorus (P), a group 5 element, was used as the dopant to prepare p-type zinc oxide bulk materials through cold pressing and two-stage high-temperature sintering. The crystallinity, morphology, and elemental composition of the ZnO powder were analyzed using X-ray diffraction (XRD), Raman spectroscopy, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS).Experimental results indicate that a phosphorus doping concentration of 0.4 at% exhibits the most stable p-type semiconductor characteristics within a temperature range of 50°C to 200°C. Simultaneously, ZnO:P powder demonstrates the optimal phosphorus p-type doping effect at a sintering temperature of 1100°C. Research into the sintering atmosphere shows that while a vacuum environment helps maintain stable p-type characteristics and low resistivity, an oxygen-rich environment effectively suppresses n-type intrinsic defects, making it highly suitable for fabricating MOSFET substrates. Regarding device fabrication, this study successfully fabricated n-type ZnO MOSFETs on p-type bulk ZnO substrates. Furthermore, for Ga2O3, a fourth-generation semiconductor with superior wide-bandgap characteristics, a liquid metal lift-off transfer method was utilized to produce ultrathin channel materials for n-type Ga2O3 MOSFETs. By optimizing the p-type doping process and transistor fabrication parameters, this research provides a feasible technological path for advanced energy management in high-performance electronic systems.

硼在氮化鎵高電子遷移率電晶體中的應用與影響;The Applications and Impacts of Boron in Gallium Nitride High Electron Mobility Transistors

title: 硼在氮化鎵高電子遷移率電晶體中的應用與影響;The Applications and Impacts of Boron in Gallium Nitride High Electron Mobility Transistors abstract: 本論文研究專注在有機金屬化學氣相沉積系統(MOCVD)成長氮化鎵高電子遷移率電晶體(GaN HEMT transistor)於低阻(111)矽基板上。本研究突破過去僅以碳(Carbon)或鐵(Iron)摻雜在氮化鎵緩衝層的方式，提出將硼摻雜在氮化鎵緩衝層，並發現以傳統連續成長的方式會造成成長模式由原先的Stranski–Krastanov (SK) 模式轉變為 Volmer–Weber (VW) 島狀成長並發生品質劣化的問題。故我們提出delta doping的摻雜方式將硼在不改變理想模式的情況下加入1200 V高功率結構的GaN緩衝層中，引入10對單原子層高濃度硼摻雜。實驗結果顯示，當崩潰電流密度定義為0.1 A/cm2時，崩潰電壓則由參考樣品的398 V顯著提升至975 V。另外在氮化硼鎵下位障層(BGaN back barrier)研究方面，首次將足夠厚的氮化硼鎵下位障層引入高電子遷移率電晶體中，並成功優化理想成長條件為12 nm的 B0.015Ga0.985N，補足過去在理論模擬與實際元件應用之間的差距。在元件表現上，相對於參考樣品，引入下位障層後，臨界電壓從1.7 V上升至2.1 V，Ion/Ioff ratio由3.21×108上升至1.27×109，VG = -3時閘極漏電流(IG)由5.927×10-7 mA/mm下降至7.54×10-8 mA/mm，垂直崩潰電壓由1210 V 提升至1275 V ; 在 Drain lag 量測中，動態導通電阻僅上升至 1.7 倍，且水平方向崩潰電壓最高可達 1491 V 並伴隨較低漏電流斜率，證實BGaN下位障層設計具有高阻值特性與提升載子侷限性能力。;This thesis focuses on the growth of GaN high electron mobility tran-sistors (HEMTs) on low resistivity (111) Si substrates by metal organic chemical vapor deposition (MOCVD). Beyond the conventional approach of employing carbon or iron doping in the GaN buffer, we propose the incor-poration of boron into the GaN buffer layer. However, it is found that con-ventional continuous growth leads to a transition of the growth mode from the Stranski–Krastanov (SK) mode to a Volmer–Weber (VW) island growth mode, resulting in degraded crystalline quality. To address this issue, a boron delta doping scheme is introduced into the GaN buffer of a 1200 V high-power structure, where 10 pairs of monolayer level, heavily bo-ron-doped layers are embedded without disturbing the desired growth mode. Experimental results show that, under a breakdown current density criterion of 0.1 A/cm², the breakdown voltage is significantly enhanced from 398 V in the reference sample to 975 V. For the BGaN back barrier (BGaN BB) study, a sufficiently thick BGaN back barrier is incorporated for the first time into a HEMT structure, and the optimal growth condition is identified as a 12 nm thick B0.015Ga0.985N layer, thereby helping to bridge the gap between previous theoretical simulations and practical device implementation. In terms of device performance, compared with the reference sample, the introduction of the BGaN back barrier increases the threshold voltage from 1.7 V to 2.1 V and improves the Ion/Ioff ratio from 3.21×108 to 1.27×109. The gate leakage current IG at VG = −3 V is reduced from 5.927×10-7 mA/mm to 7.54×10-8 mA/mm, while the vertical breakdown voltage is enhanced from 1210 V to 1275 V. In Drain lag measurement, the dynamic on-resistance increases only to 1.7 times its static value, and the lateral breakdown voltage reaches as high as 1491 V with a reduced leakage current slope, confirming the high resistivity of the BGaN layer and its effectiveness in strengthening carrier confinement.