設計具誤差消除機制之串疊式三角積分調變器; The Design of Cascaded Sigma-Delta Modulator with DAC Error Cancellation Scheme

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Title:	設計具誤差消除機制之串疊式三角積分調變器;The Design of Cascaded Sigma-Delta Modulator with DAC Error Cancellation Scheme
Authors:	林嘉文;Chia-wen Lin
Contributors:	電機工程研究所
Keywords:	三角積分;調變器;類比轉換器;多位元;ADC;modulator;multibit;sigma-delta
Date:	2008-07-08
Issue Date:	2009-09-22 12:05:53 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	三角積分調變器已廣泛的應用在類比和數位介面間的資料轉換，如語音和通訊系統上的應用。相較於其他架構類比數會轉換器，三角積分調變器能達到較高的解析度同時對所組成電路的要求也較低，而且電路複雜度也較為簡單了。對於高階多位元三角積分調變器架構來說，回授路徑上的數類比轉換器由於元件間不匹配造成的線性度問題，往往會決定了整體電路系統性能的好壞。因而發展出許多的額外的電路機制，來降低此數位類比換器產生的雜訊，有效的改善高階多位元三角積分調變器架構的效能。本論文提出一個有效消除回授路徑上數類比轉換器產生的誤差，大為降低此誤差對電路系統的影響。該電路以全差動交換式電容電路架構設計，透過TSMC 0.18μm製程，GSM通訊系統的規格來實現、驗證所提出的電路架構。 Sigma-delta modulators are widely used to implement the interface between analog and digital signal in data converters, such as audio and communication systems. The delta-sigma modulator is relatively insensitive to imperfections in circuit components and offers many advantages for realization of high-resolution analog to digital converters, and complexity of the analog circuits is much simple in comparison with Nyquist-rate converters. For the high-order cascade multibit sigma-delta modulator, the linearity of the internal DAC in the feedback path will determine the performance of overall system. Various additional circuits have been proposed to improve the performance by suppressing the noise. In this thesis, we propose an improvement to suppress the performance degradation caused by nonlinearity of DAC. The circuit is implemented with fully differential switch-capacitor circuitry and simulated by the TSMC 0.18μm process. The experimental modulator is implemented over 200kHz bandwidth in GSM system specification to verify the proposed architecture.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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