摘要： The recently proposed GPGPU architecture has added a multi-level hierarchy of shared cache to better exploit the data locality of general purpose applications. The GPGPU design philosophy allocates most of the chip area to processing cores, and thus results in a relatively small cache shared by a large number of cores when compared with conventional multi-core CPUs. Applying a proper thread mapping scheme is crucial for gaining from constructive cache sharing and avoiding resource contention among thousands of threads. However, due to the significant differences on architectures and programming models, the existing thread mapping approaches for multi-core CPUs do not perform as effective on GPGPUs. This paper proposes a formal model to capture both the characteristics of threads as well as the cache sharing behavior of multi-level shared cache. With appropriate proofs, the model forms a solid theoretical foundation beneath the proposed cache hierarchy aware thread mapping methodology for multi-level shared cache GPGPUs. The experiments reveal that the three-staged thread mapping methodology can successfully improve the data reuse on each cache level of GPGPUs and achieve an average of 2.3× to 4.3× runtime enhancement when compared with existing approaches. 其他題名： TC 出版者： New York: IEEE 出版日期： 2015-04 出處： IEEE Transactions on Computers, 2015-04, Vol.64 (4), p.884-898 資源來源： IEEE Xplore (NTUSG) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Apr 2015 識別號： ISSN: 0018-9340 識別號： EISSN: 1557-9956 識別號： DOI: 10.1109/TC.2014.2308179 識別號： CODEN: ITCOB4
