Maruzen Co., Ltd/Maruzen Kabushikikaisha;The Institute of Electronics, Information and Communication Engineers
摘要:
摘要： The notion of multiple constant multiplication (MCM) is extensively adopted in digital signal processing (DSP) applications such as finite impulse filter (FIR) designs. A set of adders is utilized to replace regular multipliers for the multiplications between input data and constant filter coefficients. Though many algorithms have been proposed to reduce the total number of adders in an MCM block for area minimization, they do not consider the actual bitwidth of each adder, which may not estimate the hardware cost well enough. Therefore, in this article we propose a bitwidth-aware MCM optimization algorithm that focuses on minimizing the total number of adder bits rather than the adder count. It first builds a subexpression graph based on the given coefficients, derives a set of constraints for adder bitwidth minimization, and then optimally solves the problem through integer linear programming (ILP). Experimental results show that the proposed algorithm can effectively reduce the required adder bit count and outperforms the existing state-of-the-art techniques. 其他題名： IEICE Trans. Fundamentals 出版者： The Institute of Electronics, Information and Communication Engineers 出版日期： 2014 出處： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2014/04/01, Vol.E97.A(4), pp.931-939 資源來源： J-STAGE Free 版權： 2014 The Institute of Electronics, Information and Communication Engineers 識別號： ISSN: 1745-1337 識別號： ISSN: 0916-8508 識別號： EISSN: 1745-1337 識別號： DOI: 10.1587/transfun.E97.A.931
