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    請使用永久網址來引用或連結此文件: https://ir.lib.ncu.edu.tw/handle/987654321/106220


    題名: A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC
    作者: 鄭國興;Tu, Yo-Hao;Huang, Hong-Yi;Cheng, Kuo-Hsing;Liu, Jen-Chieh;Hu, Chang-Chien
    貢獻者: 資訊電機學院電機工程學系
    關鍵詞: all-digital phase-locked loop (ADPLL);digital controlled oscillator (DCO);low supply voltage;multi-phase outputs;time amplifier (TA);time-to-digital converter (TDC)
    日期: 2015-12-22
    上傳時間: 2026-04-23 13:14:08 (UTC+8)
    出版者: The Institute of Electronics, Information and Communication Engineers (IEICE);The Institute of Electronics, Information and Communication Engineers
    摘要: 摘要: This paper proposes an 8-phase all-digital phase-locked loop (ADPLL) for a low supply voltage application. The proposed multi-phase digitally controlled oscillator (MP-DCO) employs two sub-feedback loops at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme, which reduces its area, and uses a time amplifier to extend the timing resolution. With a low supply voltage, the DCO and the sense-amplifier based delay flip-flop (SA-DFF) use bulk-controlled techniques to improve the performance at high operational frequencies and setup/hold times, respectively. When the ADPLL output is 1.6 GHz at 0.6 V, the RMS and peak-to-peak jitters are 3.8 ps and 33.7 ps, respectively. The power consumption and core area are 9.1 mW at 1.6 GHz and 0.036 mm2 in a 90 nm CMOS process, respectively. Thus, this clock generator is useful for low power systems.
    其他題名: IEICE Electron. Express
    出版者: The Institute of Electronics, Information and Communication Engineers
    出版日期: 2016
    出處: IEICE Electronics Express, 2016, Vol.13(2), pp.20150950-20150950
    版權: 2016 by The Institute of Electronics, Information and Communication Engineers
    識別號: ISSN: 1349-2543
    識別號: ISSN: 1349-9467
    識別號: EISSN: 1349-2543
    識別號: EISSN: 1349-9467
    識別號: DOI: 10.1587/elex.12.20150950
    顯示於類別:[電機工程學系] 期刊論文

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