Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:
摘要： This paper proposes an ultra-low-voltage all-digital phase-locked loop (ADPLL) with a digital supply regulator (DSR). The DSR maintains an RMS jitter for a 280-MHz output signal of less than 0.55% when a 100-kHz to 100-MHz supply noise is produced on a digitally controlled oscillator (DCO). The DCO uses the two-step timing resolution of a digitally controlled varactor to achieve the high timing resolution. The proposed digital loop filter can reduce the area cost and critical path using the double-edge trigger technique. For a low supply voltage, the DCO and the time-to-digital converter use bulk-controlled techniques to increase the highest operating frequency and timing resolution, respectively. When the ADPLL output is 800 MHz at 0.6 V, the power consumption and core area are 656 μW and 0.02 mm 2 , respectively, in a 90-nm CMOS process. 其他題名： TCSII 出版者： New York: IEEE 出版日期： 2012-12-01 出處： IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.888-892 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Dec 2012 識別號： ISSN: 1549-7747 識別號： EISSN: 1558-3791 識別號： DOI: 10.1109/TCSII.2012.2231021 識別號： CODEN: ICSPE5
