Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:
摘要： This letter presents a K-band CMOS power amplifier that adopted a unilateralized technique to mitigate the intrinsic gate-drain feedback effect of the transistor for increasing the reverse isolation and power gain. This three-differential-stage amplifier used low-loss transmission-line transformers (TLTs) for the input/output impedance matching networks and the transformers (TFs) for the inter-stage coupling. The obtained 3-dB bandwidth is from 18.8 to 23.3 GHz with better than 58-dB reverse isolation. The amplifier achieves a power gain of 26.2 dB, a saturation output power of 20.3 dBm, an output 1-dB gain compression point of 17.2 dBm and power added efficiency (PAE) of 24.1% under a power consumption of 440 mW. The chip size is 1.12 mm 2 including all pads. 其他題名： LMWC 出版者： New York: IEEE 出版日期： 2016-11 出處： IEEE Microwave and Wireless Components Letters, 2016-11, Vol.26 (11), p.924-926 資源來源： IEEE/IET Electronic Library 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016 識別號： ISSN: 1531-1309 識別號： ISSN: 2771-957X 識別號： EISSN: 1558-1764 識別號： EISSN: 2771-9588 識別號： DOI: 10.1109/LMWC.2016.2615028 識別號： CODEN: IMWCBJ
