Institute of Electrical and Electronics Engineers Inc.;IEEE
摘要:
摘要： Design and analysis of low-phase-noise low-jitter subharmonically injection-locked voltage-controlled oscillator (VCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90-nm CMOS process. The issue of the narrow locking range for the subharmonically injection-locked VCO (SILVCO) can be resolved over the variations, especially for high subharmonic number and millimeter-wave band, since the control voltage is adaptively adjusted using the proposed innovative method to refer to the subharmonic input frequency. A theoretical model of the SILVCO with FLL self-alignment technique is addressed for the design consideration and phase noise evaluation. With a subharmonic number of 16, the operation frequency of the proposed K -band circuit is from 24 to 26.1 GHz. The measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are -114.3 dBc/Hz and 56.6 fs, respectively. As the temperature is from 20 °C to 70 °C, the measured deviations of output power, phase noise, and jitter are within 2 dB, 3 dB, and 67 fs, respectively. This paper demonstrates excellent performance and good robustness, and it can be compared with the previously reported state-of-the-art clock generators in silicon-based technologies. 其他題名： TMTT 出版者： IEEE 出版日期： 2016-12 出處： IEEE transactions on microwave theory and techniques, 2016-12, Vol.64 (12), p.4632-4645 資源來源： IEEE Electronic Library (IEL) 識別號： ISSN: 0018-9480 識別號： EISSN: 1557-9670 識別號： DOI: 10.1109/TMTT.2016.2623784 識別號： CODEN: IETMAB
