Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
摘要:
摘要： The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array. 其他題名： TVLSI 出版者： New York, NY: IEEE 出版日期： 2012-04-01 出處： IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012-04, Vol.20 (4), p.673-683 資源來源： IEEE Electronic Library (IEL) 版權： 2015 INIST-CNRS 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Apr 2012 識別號： ISSN: 1063-8210 識別號： EISSN: 1557-9999 識別號： DOI: 10.1109/TVLSI.2011.2107533 識別號： CODEN: IEVSE9
