A Scalable Digitalized Buffer for Gigabit I/O

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > journal & Dissertation > Item 987654321/31772

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/31772

Title:	A Scalable Digitalized Buffer for Gigabit I/O
Authors:	Lu,HungWen;Su,ChauChin;Liu,Chien-Nan
Contributors:	電機工程研究所
Keywords:	AC
Date:	2008
Issue Date:	2010-07-06 18:11:15 (UTC+8)
Publisher:	中央大學
Abstract:	A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSM
Relation:	PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

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