在奈米製程下考量效能和可製造性之多階層無格線式全晶片繞線;Multilevel Gridless Full-Chip Routing for Performance and Manufacturability for Nanometer Technologies

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/57382

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/57382

Title:	在奈米製程下考量效能和可製造性之多階層無格線式全晶片繞線;Multilevel Gridless Full-Chip Routing for Performance and Manufacturability for Nanometer Technologies
Authors:	陳泰蓁
Contributors:	中央大學電機工程學系
Keywords:	電子電機工程類;實體設計;繞線;無格線式繞線;多階層架構;可製造性設計 physical design;routing;gridless routing;multilevel framework;design for manufacturability (DFM)
Date:	2008-09-01
Issue Date:	2012-10-01 15:19:39 (UTC+8)
Publisher:	行政院國家科學委員會
Abstract:	隨著製程技術進入奈米（nanometer）時代，晶片上元件的尺寸縮小到90奈米以下，同時，單顆晶片可容納超過十億個電晶體。再者，元件的最小尺寸比微影技術（lithography）所使用的波長小上許多，因此晶圓上的設計形狀可能有很大的失真（distortion）。為了處理如此龐大又複雜的電路設計，需要發展新的繞線系統（routing system）來處理現代設計的四大挑戰：複雜度（complexity）、可繞度（routability）、晶片效能（performance）以及可製造性（manufacturability）。本計畫旨在提出了一個多階層（multilevel）無格線式（gridless）全晶片繞線系統以解決這四大挑戰。我們計畫以三個重要研究主題依序進行研究：一、無格線式繞線模型：為了解決現代繞線以及奈米電氣效應的問題，電路設計需要使用可變線寬（variable-width）以及可變線距（variable-spacing）。因此，需要無格線式的繞線方法，因為它具有高度的彈性來處理可變線寬以及可變線距。我們計畫提出一個無格線式繞線模型，可以避免最後的繞線路徑違反設計規則（design rule）以及避免產生多餘的線段（wire）。二、多階層架構（framework）：為了解決日益增加的設計複雜度，需要新一代的電子設計自動化多階層架構。我們計畫提出一個新的多階層架構來提升晶片效能，這個多階層架構運作的方式為：由上而下（top-down）的反粗糙化（uncoarsening）接著是自下而上（bottom-up）的粗糙化（coarsening）。三、光學鄰近校正（Optical-Proximity Correction, OPC）模型：由於次波長的微影技術，製造90奈米以下的元件需要密集地使用解析度增強技術（Resolution-Enhancement Techniques, RET’s），而光學鄰近校正是工業界中最常使用的技術。在繞線階段考慮光學鄰近校正，可以大幅減少後佈局（post-layout）階段執行光學鄰近校正的成本。我們計畫提出一個以模型為基礎（model-based）的模型來預測後佈局階段光學鄰近校正軟體的行為，並且把提出的模型整合進入我們的多階層無格線式繞線器以降低光學鄰近校正的成本。 ; As technology advances into the nanometer era, chips may consist of billions of transistors, and process geometries shrink to 90 nm and below. Further, the minimum feature size becomes significantly smaller than the lithographic wavelength, and thus design shapes on a wafer may have large distortions. For such large and complex designs, it is desirable to develop a new routing system that can cope with the four major modern design challenges: complexity, routability, performance, and manufacturability. In this project, we propose a multilevel gridless full-chip routing system to handle these four design challenges. We intend to develop three major techniques: 1. Gridless Routing Model: To handle modern routing with nanometer electrical effects, we need to consider designs with variable wire/via widths and spacings, for which gridless routing approaches are desirable due to its great flexibility. We intend to propose a gridless routing model that can obtain design-rule-correct paths and avoid redundant wires. 2. Multilevel Framework: To cope with the increasing complexity, new multilevel frameworks of next generation electronic design automation for nanometer designs are needed. We intend to present a new multilevel framework for performance consideration. The new framework works in the following manner: top-down uncoarsening followed by bottom-up coarsening. 3. Optical Proximity Correction (OPC) modeling: Due to the sub-wavelength lithography, manufacturing the sub-90 nm feature size requires intensive use of Resolution-Enhancement Techniques (RET's), among which OPC is the most popular technique in industry. Considering OPC during routing can significantly alleviate the cost of post-layout OPC operations. We intend to present a model-based OPC modeling to predict the behavior of a post-layout OPC tool and incorporate the models into our gridless router to reduce the OPC cost. ; 研究期間 9709 ~ 9807
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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