雙閘極P通道無接面場效電晶體之模擬與分析; Analysis and Simulation of Double-Gate P-Channel Junctionless MOSFET

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/61173

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/61173

Title:	雙閘極P通道無接面場效電晶體之模擬與分析;Analysis and Simulation of Double-Gate P-Channel Junctionless MOSFET
Authors:	辛信億;Hsin,Hsin-Yi
Contributors:	電機工程學系
Keywords:	無接面;無接面場效電晶體;雙閘極P通道無接面場效電晶體;Junctionless;Junctionless MOSFET;Double-Gate P-Channel Junctionless MOSFET
Date:	2013-07-02
Issue Date:	2013-08-22 12:13:57 (UTC+8)
Publisher:	國立中央大學
Abstract:	在本篇論文中，首先介紹無接面電晶體的基本操作原理與優點，我們利用二維元件模擬來模擬無接面電晶體元件內部的電位分佈，並且可由電位分佈看出空乏區從未導通到聚積的變化，我們同時利用Poisson’s equation推導出臨限電壓公式與空乏層大小，再利用空乏層大小推導出電流公式，並且將此推導結果與我們利用二維元件模擬器得到的模擬結果做比較，以及我們改變各項參數來觀察對臨限電壓與汲極電流的影響，最後我們在模擬CMOS無接面電晶體在短通道下的開關特性，並且討論無接面電晶體在次臨限區域時，其次臨限擺幅與傳統場效電晶體的比較。 In the thesis, at first we introduce the basic operating principles and advantages of the junctionless transistor. We use the two-dimensional device simulation to simulate the potential distribution of the junctionless transistor and then we get the variation of depletion region from turn-off to accumulation. We try to derive the threshold voltage and depletion layer thickness equation from Poisson’s equation, and furthermore figure out the drain current equation. We compare the equations with the result obtained by 2D numerical device simulation, and we change the parameters to observe effects of threshold voltage and drain current. At last, we simulate the switching characteristics of the short channel CMOS junctionless transistor. We compare the subthreshold swing of the junctionless transistor with a normal transistor in subthreshold region.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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