本篇論文主要設計導向為應用於V-頻段射頻收發機前端電路之源極注入式混頻器之設計與研製，論文主軸包含一顆主動式升頻混頻器以及一顆主動式降頻混頻器，並以90奈米互補式金屬氧化物半導體製程研製而成。整體電路設計概念主要以低電壓及低功率消耗操作之應用，並以高轉換增益、良好線性度與較佳隔離度等方向作為設計目標。 本篇論文第三章提出一顆低電壓、低功率消耗操作之新式升頻混頻器電路並以台積電(TSMC)標準90奈米互補式金屬氧化物半導體製程研製而成，主要電路架構由偽差動對源極注入式混頻器電路以及電流再生技術所建構而成。在電路設計概念上，將升頻混頻器電路操作於接近弱反轉區，使得整體電路在供應電壓為0.4 V時，其消耗功率只有149 W，同時，此混頻器電路亦可在毫米波頻段上保有較佳之電路性能。此電路架構經由實際量測後可獲得-0.62 dB之轉換增益(conversion gain)與-4 dBm之輸出三階截斷點(output third-intercept point: OIP3)且其3-dB操作頻寬範圍為17.5至22.3 GHz。在供應電壓為0.3 V時，整體電路之最佳性能指數(Figure of Merit : FOMUp-M)經由計算可達到33.2。此外，整體晶片尺寸大小為0.72 mm2。 第四章則是介紹一顆微瓦特源極注入式降頻混頻器結合一寬頻非對稱式堆疊耦合架構之馬遜巴倫並以聯電(UMC)低功率90奈米互補式金屬氧化物半導體製程研製而成。在電路設計概念上，此降頻混頻器採用基體偏壓控制技術進而降低整體電路所需之臨界電壓(threshold voltage VTH)與供應電壓，藉以達到此毫米波主動式降頻混頻器能操作在接近於弱反轉區之設計目標。再者，為有效縮小整體電路晶片尺寸大小，本篇論文成功研製出一顆寬頻非對稱式堆疊耦合架構之馬遜巴倫，整體3-dB頻寬可達到103 GHz (頻寬範圍從34 GHz至137 GHz)，且在58 GHz時，此巴倫具有3.66 dB之最低插入損耗(3 dB為理想插入損耗值)。而整體馬遜巴倫之晶片尺寸大小為0.016 mm2。經由實際電路量測後，此降頻混頻器在55 GHz時可獲得4.2 dB之最高轉換增益與14.3 dBm之輸入三階截斷點(input third-intercept point: IIP3)。此時，其本地振盪輸入功率(LO power)為2 dBm。在供應電壓為0.5 V時，所流過之直流電流為278 A且整體電路之消耗功率只有139 W。整體降頻混頻器電路之晶片尺寸大小為0.72 mm2，其中亦包含兩顆非對稱式堆疊耦合架構之馬遜巴倫。此外，所提出之源極注入式降頻混頻器可有效操作在低供應電壓及低消耗功率之應用下，因此，其最佳性能指數(FOMDown-M1)可達到39.1。 This thesis is primarily targeted to design and implement the key component, mixer, for V-band radio frequency (RF) transceiver front-end using source-driven technology. There are two source-driven mixers are investigated based on 90-nm CMOS process that include both up-conversion and down-conversion topologies. The main design goals aim towards high conversion gain (CG), linearity, and port-to-port isolations under ultra-low voltage low power operations. In the thesis, Chapter 3 proposes a novel up-conversion mixer with pseudo-differential and current-reused topology in TSMC standard 90 nm CMOS technology. The proposed source-pumped up-conversion mixer can operate at near weak inversion under a power consumption of 149 W from a 0.4-V supply voltage while maintains acceptable circuit performance at millimeter-wave (MMW) frequencies. The up-conversion mixer achieves a -0.62 dB conversion gain and a -4 dBm OIP3 in measurements. The measured 3-dB frequency bandwidth ranges from 17.3 to 22.5 GHz. The best figure-of-merit (FOMUp-M) acquires as high as 33.2 under a 0.3-V supply. The chip size including all pads and dummy blocks is 0.72 mm2. Chapter 4 proposes a microwatt (W) source-driven down-conversion mixer with broadband asymmetrical broadside-coupled baluns in UMC 90-nm CMOS low-power (LP) process. The forward body biased (FBB) technique reduces the threshold voltage (VTH) and supply voltage for operation in the near weak inversion region in MMW active mixer designs. To effectively reduce the size of the chip, an asymmetrical broadside-coupled balun is developed with a bandwidth (BW) of 103 GHz (from 34 to 137 GHz) with a low insertion loss of 3.66 dB (3 dB for an ideal balun) at 58 GHz. The chip area of the balun is 0.016 mm2. The proposed FBB mixer has a 4.2-dB peak CG and a 14.3-dBm input IP3 at 55 GHz under a 2-dBm LO power input. The DC power of the FBB mixer core is only 139 W, while it draws a 278-A DC current from a 0.5-V supply. The fabricated FBB mixer, comprising two asymmetrical broadside-coupled baluns, and all of test pads and dummy blocks, occupies an area of 0.72 mm2. An FOMDown-M2 that is obtained using the ultra-low power consumption FBB mixer is as high as 39.1.
