According to Moore’s Law, the number of transistors in the integrated circuit has double approximately every twenty-four months. With the scaling of feature size, the performance of chips will be limited not only by the electrical performance of the transistors but also by the transmission rate of interconnect. Therefore, the RC delay of back-end interconnect will be one of main issue for limiting the development of integrated circuit. [1] To enhance the transmission rate of interconnect, aluminum was replaced with copper which has lower resistivity and better ability against eletromigration. As a result, it could enhance the performance of integrated circuit. However, the diffusion coefficient of copper is very large, and it is easy for copper to diffuse into silicon substrate. It is a great issue that how to enhance diffusion barrier and electromigration when we scale down the width of interconnect and hold up high current density. [2]
In the research, lithography and deposition process were employed to fabricate interconnect with TaMn alloy as diffusion barrier and Cu3Ge alloy as seed layer of plating. The failure time of different test structure was measured by high current density and high temperature. By this method, the activation energy and current acceleration factor can be obtained. To compare with the samples with diffusion barrier of TaN/Ta, interconnect reliability with different diffusion barriers and seeding layer was summarized and the mechanism of the failure mode was analyzed.
