隨著半導體產業和電腦相關產業的快速發展，且高速串列傳輸系統也廣泛被使用，所以資料的傳遞速度日漸提升。在高速串列傳輸系統中，時脈與資料回復電路扮演了還原時脈和輸入資料時序上的問題，也因為資料速率的增加，電路的時間容忍區間會變得非常小，難以確保時脈與資料回復電路有好的誤碼率和抖動容忍度，所以如何降低資料上誤碼率的發生是現今必須克服的問題。 本論文將參考USB 3.0規範並提出一個具自適應迴路增益控制器和數位式電容放大技術之雙路徑時脈與資料回復電路，透過自適應迴路增益控制器偵測輸入抖動之頻率資訊來調整系統迴路增益，可優化系統的產生的抖動和抖動容忍度，改善了50 %的低頻抖動容忍度和12 %高頻抖動容忍度。數位式電容放大器去累積二進位相位偵測器之輸出訊號，因此使用的電容值從205 pF減少到3.2 pF，所以減少了50 %的面積成本並且可維持原有的系統穩定度。本論文使用90 nm標準CMOS製程來實現，電路操作電壓為1 V，晶片面積為0.073 mm2，輸入資料速率為5 Gbps時，還原時脈的峰對峰值抖動為26.4 pspp，和方均根值抖動為3.2 psrms，消耗功率為16.8 mW。 ;As CMOS technology continues to advance, the computing capabilities of integrated circuits are expanding, and the fast serial link technologies have received significant attention in the recent past. The clock and data recovery (CDR) is the crucial role of receiver timing circuits in the serial link systems, and achieves to optimally sample the input data with various timing jitter profiles. Due to increasing of the data rate, the timing budget of the CDR becomes very tight and makes it more difficult to guarantee the required Bit-Error-Rate (BER) and the jitter tolerance (JTOL). This study takes USB 3.0 specification as reference material, and presents a dual path clock and data recovery with adaptive loop gain controller (ALGC) and capacitor-amplified technique (CA). The ALGC enhances the jitter performance and JTOL by detecting the jitter frequency spectrum and controlling loop gain adaptively, and the enhanced percentage of low and high frequency input jitter is about 50% and 12%, respectively. To reduce the area of loop filter, the CA is utilized in the integral path to count the output signal of the bang-bang phase detector, and the reduced percentage of area is about 50% without lowering system stability. The test chip was fabricated by a 90-nm standard CMOS process with a 1-V supply and the core area occupies 0.073 mm2. The measured jitter of the recovered clock is 3.2 psrms and 26.4 pspp, and the power consumption is 16.8 mW at the 5-Gbps data rate.
